Analog CMOS IC layout: DRC, DFM, DFR

Thread Starter

Tako

Joined Oct 21, 2014
65
Regarding CMOS analog IC layout, what are differences between DRC, DFM and DFR?

What I understood during research:
- DRC (Design Rule Check)
checks if a laid out block follows technology rules what ensures dimensional precision and electrical parameters

- DFM (Design For Manufacturing)
additional check on top of DRC. Additional rigorous rules to further increase yield comparing to DRC.

Depending on technology, particular check rules may be included in DRC or DFM, e.g.: antenna effect check may be in DRC or DFM of a given technology in a given foundry.

Is, what I wrote above, correct?

What is DFR (Design For Reliability)? Is that just synonym of DFM?
 

dl324

Joined Mar 30, 2015
10,758
Is, what I wrote above, correct?
Yes, for as far as you went.

DRC also includes connectivity verification (sometimes called layout vs schematic - LVS). Design rules can also include rules that improve yield (e.g. antenna rules/node area checks).

DFM encompasses a range of things. It could be only using the tightest rules when necessary or laying out transistors so that process variation wouldn't have a significant affect on matching.
What is DFR (Design For Reliability)? Is that just synonym of DFM?
Where I worked, we called it RV (Reliability Verification). This would involve simulating the design under worst case conditions (e.g. maximum frequency) and checking for problems with electromigration and self heat. That requires identifying current direction in conductors.

There's also performance verification (PV). This would include things like looking for speed paths or multicycle paths.

https://www.edn.com/basics-of-multi-cycle-false-paths/
 

Thread Starter

Tako

Joined Oct 21, 2014
65
Thank you for your help. I have additional questions:


DRC also includes connectivity verification (sometimes called layout vs schematic - LVS).
But LVS is a separate verification. During layout a layout designer performs DRC regularly. After the layout is finished, LVS is performed to check whether the layout is equal with the schematic (all devices from schematic are on the layout and the connectivity between devices is the same).


Design rules can also include rules that improve yield (e.g. antenna rules/node area checks).
So such checks as antenna rules etc. may be either in DRC or DFM?


Where I worked, we called it RV (Reliability Verification). This would involve simulating the design under worst case conditions (e.g. maximum frequency) and checking for problems with electromigration and self heat. That requires identifying current direction in conductors.
From what you wrote, RV is a post-layout verification.


There's also performance verification (PV).
What PV stands for?
 

jpanhalt

Joined Jan 18, 2008
9,426
But LVS is a separate verification. During layout a layout designer performs DRC regularly. After the layout is finished, LVS is performed to check whether the layout is equal with the schematic (all devices from schematic are on the layout and the connectivity between devices is the same).
I interpreted your question to be what the acronyms meant. Some of your comments seem to apply to specific CAD software. For example, with EAGLE (v. prior to 8), there is no way to created a PCB and not have all the components from the schematic in it. There are warnings, even for insignificant parts such as vias. If one does a workaround to avoid such warnings for actual parts, the program gives a banner warning the board and schematic are not consistent. So, there is no LVS per se. There are only DRC and ERC.
 

dl324

Joined Mar 30, 2015
10,758
But LVS is a separate verification. During layout a layout designer performs DRC regularly. After the layout is finished, LVS is performed to check whether the layout is equal with the schematic (all devices from schematic are on the layout and the connectivity between devices is the same).
Your right. LVS is more correctly part of layout verification. Some layout designers run it when they think they're finished. Others will run it more often so they can correct connectivity and design rule problems at the same time.

Personally, I don't think it makes much sense to keep running only DRC's and later find that you had connectivity problems that require ripping up layout and re-doing it.
So such checks as antenna rules etc. may be either in DRC or DFM?
Antenna rules are to avoid damage caused by processing the wafers and are specified by the group who defines the design rules. Since it's part of the process work flow, it was included in the design rules where I worked. It made sense because engineering often knew little about how the wafers were processed and the physics involved.

DFM is mainly up to the projects. They could always use minimum design rules, but not doing that can increase yield. That's what I consider DFM. Adding redundant contacts and vias, increasing enclosure/space, matching device layout so process variation didn't affect device performance, extending endcaps are common DFM rules.

From what you wrote, RV is a post-layout verification.
It doesn't have to be exclusively post layout. You can only do RV on the full chip if it's relatively small. If you're working on a design with hundreds of millions of transistors, you have to run it on smaller blocks. You can run RV when the layout is nearing completion, or you can wait. Waiting too long will put RV in the critical path to tapeout.
What PV stands for?
Performance Verification. The primary objective is to determine whether the design will operate at the intended speed.
 

Thread Starter

Tako

Joined Oct 21, 2014
65
I interpreted your question to be what the acronyms meant. Some of your comments seem to apply to specific CAD software.
As I wrote in the 1st post: "Regarding CMOS analog IC layout, what are differences between DRC, DFM and DFR?"
Hence, I am interested in DRC, DFM and DFR from analog CMOS IC layout design perspective. For EDA, we analog/layout designers work in e.g.: Cadence, Synopsys, Silvaco.
As an analog IC designer, so far, I did layouts where I did only DRC check. I wanted to research more about layout design and met DFM and DFR and I not fully understand what they add on top of DRC check.


@dl324
Thank you for your comments and explanations. I think I understand more now.

Regarding RV, checks as:
- simulating the design under worst case conditions (e.g. maximum frequency)
- checking for problems with electromigration and self heat
sounds to me as simulations done by analog IC designer. Not as procedures run from EDA tool (Cadence, Silvaco, Synopsys) as DRC or LVS done by layout IC designer. So I would rather put RV in the general full IC design flow as post-layout simulations and not in the strict layout flow.
 

dl324

Joined Mar 30, 2015
10,758
sounds to me as simulations done by analog IC designer.
Where I worked, at around the 65nm node, there wasn't much difference between analog and digital layout. Before that, analog used more transistor Z/L combinations.

I was never too deeply involved with RV or PV; my responsibility was LV. I don't think we used tools from the EDA vendors for those areas. Our company was large enough that we could develop our own tools if nothing suitable was available commercially.
 

andrewmm

Joined Feb 25, 2011
326
assuming this is not just a home work question,

IMHO

review and change is constant in the design process.
This is double true now days when designs are not "chucked over the wall" at each stage, but all but done in parallel.

e.g. If a reliability issue is thought about at the design stage, its corrected then, not later at review.

its like a flow chart, top to bottom, at each stage reviews are done,
you aim to at worse have an issue that does not need one to step back a stage,

It the old old conundrum

top down or bottom up design,
in the real world , you do both at the same time,
 

dl324

Joined Mar 30, 2015
10,758
Incidentally, the first time I did layout, it was for a 0.7um GaAs process for MSI digital circuits and all verification was done manually. Programs existed, but were relatively crude. The largest layout I did was 1000um on a side. At that time, the primary methods for doing layout were cutting "ruby" or drawing on green grid and having that "digitized". I was fortunate to have an Applicon AGS/870 system that let you enter layout using a stylus.

This was late 70's and the computer system cost was around $500K. CMOS design rules didn't hit that milestone until about 25 years later.
 

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Thread Starter

Tako

Joined Oct 21, 2014
65
assuming this is not just a home work question
No, it is not XD. I wrote, I am an analog IC design engineer ;).

@dl324, OK. Thank you for your insight. :)

I think I get the differences between DRC and DFM in CMOS analog IC design. In case of further questions, I will write.
 

andrewmm

Joined Feb 25, 2011
326
No, it is not XD. I wrote, I am an analog IC design engineer ;).

@dl324, OK. Thank you for your insight. :)

I think I get the differences between DRC and DFM in CMOS analog IC design. In case of further questions, I will write.
:->

Its amazing how many hoe work question we get, under many guises,
no problem with that, but some time the teachers are way behind the times, and live in "perfect worlds" , with hard lines between processes, which don't occur in practice.
 

dl324

Joined Mar 30, 2015
10,758
I think I get the differences between DRC and DFM in CMOS analog IC design.
When I was responsible for layout verification, I would write checks for project DFM rules to run as part of DRC. I would also use the DRC checker to identify areas that manufacturing had so we could improve yield on subsequent steppings and projects.

I also defined the checks that were required for leaf cell, functional block, and unit level layout. For leaf cell, we would exclude or modify checks that weren't very relevant (e.g. metal density which became an issue when we switched from aluminum to copper).
 
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