1. Younes Thabet

    What is the use of an 3-state octal buffer/line driver?

    Hello all, I have encountered an AHC244 chip used to drive LEDs (Something like in the attached image) so I wondered why not just drive the LEDs with the uC pins? And also I have seen this IC used with some PWM signals as inputs to it! in this case, I am guessing the output would be the same...
  2. Luiz Fernando Vieira

    What is the dielectric value of the mosfet gate when hiring acceptors?

    Hello, I'm having trouble finding the value of the right concentrators that are on the gate of the gate (SiO2 as gate dielectric and P-type substrate [NA=?]) Could someone indicate a material to show a usual value?
  3. Minchuu

    CMOS low noise amplifier reference suggestions

    Hello, I want to design a CMOS Low Noise Amplifier for the frequency range 0.65 MHz to 1.45 MHz with: less than 3dB NF, ~10 dB power gain, greater than -5 dBm IIP3, and input and output impedance of 50 ohms. I am searching for references (books, sites, articles etc.) that can guide a beginner...
  4. Luiz Fernando Vieira

    Why is oxide not used in the CVD process in the manufacture of gate oxide in the NMOS device?

    I know that chemical vapor deposition (CVD) is a vacuum deposition method used to produce high-quality, high-performance solid materials. The process is often used in the manufacture of semiconductors to produce thin films, there are several CVD methods, such as LPCVD, PECVD etc. Depending on...
  5. Z

    How to interface CMOS image sensors with 32-bit Microcontrollers?

    I've been learning to program 32-bit ARM cortex-M controllers with an STM32 Nucleo (L476rg Nucleo). I've been playing with interfacing and controlling stepper motors so far. My next step is to move on to machine/computer vision and incorporate image sensing however upon some searching (hopefully...
  6. Z

    2:1 MUX in LTSpice using CMOS Transmission Gates, implementation

    Hello. I am trying to create, for a project, a 2:1 Multiplexer using CMOS Transmission gates. This MUX requires 2 transmission gates, so 4 total transistors. I have seen some implementations use an inverter when connecting the Select bus. I am pretty bad at electronics. Take a look at my...
  7. Alex_Khan

    MOSFET's model selection for different voltage source (Vdd).

    Hello, I have a question, please guide me and make me correct regarding MOSFET model selection? Although I used ‘nmos4’ both for 3.3V and 5V Vdd (supply voltage) in my simulation(cadence Virtuoso 6.1.6-64b), in both cases, it works fine and gives same results (according to my observation). So...
  8. Alex_Khan

    Obtainig Low Pass Filter's output signal as square edge.

    Hello I am demodulating a signal. In which Low Pass Filter (LPF) is used to attenuate high frequency modulated signal. The input and outup of LPF is shown. The problem is the edges of LPF output signal is not square [as shown in figure] which result in poorly selection of lower and upper...
  9. Alex_Khan

    Modulating frequency of Multi-vibrator circuit (CMOS technology)

    Hello, I am modulating control signal with Multivibrator circuit in CMOS technology. I use this formula (1/2.2RC) to find the frequency of modulated signal with multivibrator. But my simulation (result) and theoritical (calculation) of frequency is not matching. I am using CADENCE software tool...
  10. Alex_Khan

    Voltage level shifting of Signal After passing through capacitive isolation.

    Hello, May be it simple question ! but i would need the technical reason Why it happen. Problem: I am designing signal isolation circuit using capacitive coupling technique using Cadence , CMOS 0.35micro-meter technology . For that i modulate the information signal using frequency modulator on...
  11. Luiz Fernando Vieira

    Bulk fixing CMOS

    Hello everyone I'm having trouble finding the material that talks about CMOS regarding bulk fixation. I know that the bulk is welded in well n (n-well) or well p (p-well) depending on its structure, because it is welded, because it is more doped so the flow of electrons is easier this way a...
  12. T

    Analog CMOS IC layout: DRC, DFM, DFR

    Regarding CMOS analog IC layout, what are differences between DRC, DFM and DFR? What I understood during research: - DRC (Design Rule Check) checks if a laid out block follows technology rules what ensures dimensional precision and electrical parameters - DFM (Design For Manufacturing)...
  13. Luiz Fernando Vieira

    LTspice and Electric – (VLSI) - Simulation error

    I'm having trouble solving this problem with two software [LTspice and Electric - (VLSI)]. A simulation error occurs when I try to simulate. Code: C5_models.txt Source:http://cmosedu.com/videos/electric/electric_videos.htm