1. Alex_Khan

    MOSFET's model selection for different voltage source (Vdd).

    Hello, I have a question, please guide me and make me correct regarding MOSFET model selection? Although I used ‘nmos4’ both for 3.3V and 5V Vdd (supply voltage) in my simulation(cadence Virtuoso 6.1.6-64b), in both cases, it works fine and gives same results (according to my observation). So...
  2. Alex_Khan

    Obtainig Low Pass Filter's output signal as square edge.

    Hello I am demodulating a signal. In which Low Pass Filter (LPF) is used to attenuate high frequency modulated signal. The input and outup of LPF is shown. The problem is the edges of LPF output signal is not square [as shown in figure] which result in poorly selection of lower and upper...
  3. Alex_Khan

    Modulating frequency of Multi-vibrator circuit (CMOS technology)

    Hello, I am modulating control signal with Multivibrator circuit in CMOS technology. I use this formula (1/2.2RC) to find the frequency of modulated signal with multivibrator. But my simulation (result) and theoritical (calculation) of frequency is not matching. I am using CADENCE software tool...
  4. Alex_Khan

    Voltage level shifting of Signal After passing through capacitive isolation.

    Hello, May be it simple question ! but i would need the technical reason Why it happen. Problem: I am designing signal isolation circuit using capacitive coupling technique using Cadence , CMOS 0.35micro-meter technology . For that i modulate the information signal using frequency modulator on...
  5. Luiz Fernando Vieira

    Bulk fixing CMOS

    Hello everyone I'm having trouble finding the material that talks about CMOS regarding bulk fixation. I know that the bulk is welded in well n (n-well) or well p (p-well) depending on its structure, because it is welded, because it is more doped so the flow of electrons is easier this way a...
  6. T

    Analog CMOS IC layout: DRC, DFM, DFR

    Regarding CMOS analog IC layout, what are differences between DRC, DFM and DFR? What I understood during research: - DRC (Design Rule Check) checks if a laid out block follows technology rules what ensures dimensional precision and electrical parameters - DFM (Design For Manufacturing)...
  7. Luiz Fernando Vieira

    LTspice and Electric – (VLSI) - Simulation error

    I'm having trouble solving this problem with two software [LTspice and Electric - (VLSI)]. A simulation error occurs when I try to simulate. Code: C5_models.txt Source:http://cmosedu.com/videos/electric/electric_videos.htm