I am trying to calculate the width and length of each transistor in a 3-input NAND gate (NAND3) and I am getting quite confused. The gate must meet the following requirements: 1. Worst-case switching delay (rise or fall) must be between 1.6 ns and 2 ns. 2. The load capacitance is 100fF. 3. Process parameters: • K’N= 44x10^-6 A/V^2 • K’P= 13x10^-6 A/V^2 • Cox= 9x10^-4 pFμm^-2 • L= 2x10^-6 m
NAND3 Circuit Configuration decision: • NMOS Network: • 3 NMOS transistors connected in series in the pull-down path. • Effective width decreases due to the series configuration. • PMOS Network: • 3 PMOS transistors connected in parallel in the pull-up path. • Effective width increases due to the parallel configuration.
My Approach:
To calculate the transistor dimensions, I used the following delay equation:
τ= (4Cl/K’*Vdd)*L/W_eff
Worst case would be when one PMOS is on and all NMOS are on.
I wanted to know whether this is along the right lines or whether I’m heading in the complete wrong direction. Please note I am a college student and this is a practice question. Thank you so much for any help.

 

What are the transistor dimensions you are talking about?

 

Start with an initial guess for WN and verify if the delay falls within the specified range. Adjust WN and recalculate if necessary.

 

I am trying to calculate the width and length of each transistor in a 3-input NAND gate (NAND3) and I am getting quite confused. The gate must meet the following requirements: 1. Worst-case switching delay (rise or fall) must be between 1.6 ns and 2 ns. 2. The load capacitance is 100fF. 3. Process parameters: • K’N= 44x10^-6 A/V^2 • K’P= 13x10^-6 A/V^2 • Cox= 9x10^-4 pFμm^-2 • L= 2x10^-6 m
NAND3 Circuit Configuration decision: • NMOS Network: • 3 NMOS transistors connected in series in the pull-down path. • Effective width decreases due to the series configuration. • PMOS Network: • 3 PMOS transistors connected in parallel in the pull-up path. • Effective width increases due to the parallel configuration.
My Approach:
To calculate the transistor dimensions, I used the following delay equation:
τ= (4Cl/K’*Vdd)*L/W_eff
Worst case would be when one PMOS is on and all NMOS are on.
I wanted to know whether this is along the right lines or whether I’m heading in the complete wrong direction. Please note I am a college student and this is a practice question. Thank you so much for any help.

post the NAND3 schematic