1. mattmunee

    Dealing with high current traces with few layers

    I'm building a board with multiple ASIC's in series. Each ASIC has a footprint similar to a DFN, where there are a few IO pins on either side of the ASIC. In addition there are two large pads that supply power (V+) and ground (V-) for the high-current domain. Further, these ASIC's are...
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