pcie

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  1. Trumpeldor

    Industrial PCIe Gen3 (NVMe) to USB 3.2 Bridge – Part or Architecture Recommendation

    Hi everyone, I am looking for a hardware solution to bridge PCIe Gen3 (NVMe SSD) to a USB 3.2 Host, strictly requiring Industrial Temperature range (-40°C to +85°C). The Constraints: 1. Physical Interface: PCIe Gen3 (x2 or x4) to USB 3.2 Gen1/Gen2. 2. Operating Temp: -40°C to +85°C...
  2. J

    How to adjust PCIE signals using Hyperlynx S- Parameter report?

    Dear All, I’m using Hyperlynx (MentorGraphic) for Signal Integrity test for PCIE GEN 1 Tx Rx & Clk signals. I imported Altium designed layout file to Hyperlynx. This signals (Tx, Rx, Clk) don’t pass S – Parameters when I run Serdes Batch Wizard. But it pass Channel Verification. 1) What are...
  3. E

    How to change trace width and spacing of diff pairs in the design using MentorGraphics Hyperlynx SI

    Hi, I am simulating my postgraduate project using Hyperlynx SI tool. I am testing on PCIe traces of my design. I did my design using Altium and I exported to Hyperlynx file to do the simulation. But I cannot change the trace width and spacing of Differential pairs using Hyperlynx SI tool. Is...
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