@MrChips @Papabravo @ScottWang @DickCappels @Ian0 @ericgibbs @Bordodynov
Hi all, I have stumbled across this circuit. Above is a frequency divider circuit (f/3 to be exact) quoted from here. I have tried to simulate it in LT Spice and followed exactly all the connections, but no output. I believe that the problem lies within the built-in logic gate by LT Spice. Can anyone spot any misconnections or problems here as I have even tried push-pull amplifier on the output of the logic gate since it outputs a maximum of 1V only which might be insufficient by the D pins as shown above?

Thank you for reading

 

View attachment 270541
@MrChips @Papabravo @ScottWang @DickCappels @Ian0 @ericgibbs @Bordodynov
Hi all, I have stumbled across this circuit. Above is a frequency divider circuit (f/3 to be exact) quoted from here. I have tried to simulate it in LT Spice and followed exactly all the connections, but no output. I believe that the problem lies within the built-in logic gate by LT Spice. Can anyone spot any misconnections or problems here as I have even tried push-pull amplifier on the output of the logic gate since it outputs a maximum of 1V only which might be insufficient by the D pins as shown above?

Thank you for reading

I modified the three gates to have the same parameters as the flip-flops since they were using the default settings which are essentially NON-FUNCTIONAL. I lowered the voltage swing of V1 from 15V to 5V. I changed the rise and fall times of the clock to a more reasonable 10 nanoseconds, and I redefined the simulation time in terms of the clock frequency. I also cleaned up the layout getting rid of unnecessary jogs and "grayspace" .Looks OK to me. I have also posted a corrected ".asc" file.



If you want to use the plot settings file you need to remove the ".txt" extension which AAC requires for the file to be uploaded.

 

I modified the three gates to have the same parameters as the flip-flops since they were using the default settings which are essentially NON-FUNCTIONAL. I lowered the voltage swing of V1 from 15V to 5V. I changed the rise and fall times of the clock to a more reasonable 10 nanoseconds, and I redefined the simulation time in terms of the clock frequency. Looks OK to me. I have also posted a corrected ".asc" file.

View attachment 270542
If you want to use the plot settings file you need to remove the ".txt" extension which AAC requires for the file to be uploaded.

Thank you for your time and help sir

 

Thank you for your time and help sir

You're Welcome -- anytime.

 

View attachment 270467
View attachment 270468
View attachment 270469
Both pictures are quoted from here and here. I am trying to simulate it in LT Spice using Logic gates as the Level Triggered D Type Flip-flop.
However, I got the error timestep is too small in LT Spice. May I know how to solve this? Below is my LT Spice file attached.

Thank you for reading and have a nice day

Hi

The pictures are misleading.

The top NAND circuit is a level-triggered "D LATCH". The Q output will follow the state of the D input as long as the CLK input is high. This means that if the Q output is connected to D, and the CLK is high , Q output will oscillate (continuously change state between high and low) as long as the CLK is high.

The lower picture is supposed to be a edge-triggered "D Flip Flop". The output can only change state when a clock EDGE occurs. The internal circuitry is a Master/Slave arrangement so the pictures are not representative of this type of flip flop (except the symbol with the triangle at the CLK input is correct).

 

hi mrss
Is this what you are trying to do.???
Your circuit is unstable.

E
Added asc. @MrsssSu

The circuit you've shown is doing what its supposed to do. It is oscillating as long as the CLK input is high.

 

The circuit you've shown is doing what its supposed to do. It is oscillating as long as the CLK input is high.

If you took the time to read the opening post, the TS intention was to build a D type F/F not a gated 14.4MHz oscillator.

The D type was going to be used in his later posted Divider circuit.

 

If you took the time to read the opening post, the TS intention was to build a D type F/F not a gated 14.4MHz oscillator.

The D type was going to be used in his later posted Divider circuit.

Oh please....

 

Oh please....

I think you misspelled it. Isn't it "puh-leeze" in Karenspeak?

 

I think you misspelled it. Isn't it "puh-leeze" in Karenspeak?

I stand corrected...