D type flip flop truth values

ebp

Joined Feb 8, 2018
2,332
The whole circuit is just nonsense. It is nothing more than a grossly over elaborate true-complement buffer. It isn't a flip flop at all, There is no mechanism to de-assert both SET and RESET.

EDIT: The truth table and the signal drawings are both wrong. If D is 0, Q is 1.
 

Thread Starter

Brocrown

Joined Oct 14, 2018
5
The whole circuit is just nonsense. It is nothing more than a grossly over elaborate true-complement buffer. It isn't a flip flop at all, There is no mechanism to de-assert both SET and RESET.

EDIT: The truth table and the signal drawings are both wrong. If D is 0, Q is 1.
How did they get the truth values for the unclocked D-type flip flop?
 

ericgibbs

Joined Jan 29, 2010
12,884
hi,
When D is Low, Q is High and /Q is Low
When D is High, /Q is High and Q is Low

The example Truth table in the image is 'backwards' ie: wrong

E

EDIT:
Should be:
AA1 14-Oct-18 15.01.gif
 

ebp

Joined Feb 8, 2018
2,332
DeMorgan's theorem is a very useful thing. Using words for operators:

not (A and B) = (not A) or (not B)
not (A or B) = (not A) and (not B)

When you make an RS flip flop using NAND gates, it is actually a /R/S flip flop (where / indicates inversion). It is useful to apply DeMorgan's theorem and draw it as cross-coupled OR gates with inversion bubbles on each input. That way it becomes more apparent that if R is LOW, the output of the gate it goes into will be HIGH, regardless of the level of the other input, and if S is low the same applies for the gate it goes directly into.

If this were done in Figure 12.78 as in bertus's post, it would be immediately apparent that the inversion bubbles of the NAND gates at the inputs cancel those of the /R/S flip flop. It makes it easier to follow the logic at a glance.

My opinion is that by showing the circuit in your original post, the author of the book as simply thrown in something that doesn't help in understanding the gated D latch - even if the truth tables wasn't wrong.
 

crutschow

Joined Mar 14, 2008
27,170
I don't see how the first circuit can be called a flip-flop or latch as it has no memory function and does neither. :confused:
Its truth table is just that of an inverter and non-inverter.
 

WBahn

Joined Mar 31, 2012
26,398
I don't see how the first circuit can be called a flip-flop or latch as it has no memory function and does neither. :confused:
Its truth table is just that of an inverter and non-inverter.
I think the circuit shown is just meant to be an intermediate step in going from an R'S' FF to a D latch. The author either didn't realize that, without the clock suppression circuit, the input signals need to be inverted or figured that it would be too confusing to point it out. Of course, in ignoring it he made the circuit incorrect and made it even more confusing.
 

ebp

Joined Feb 8, 2018
2,332
I think a much more sensible progression would be an RS flip flop, a gated version and finally the D version.

I wouldn't call the final product "clocked" either. Maybe general parlance has changed, but that used to be a "gated latch."
 

WBahn

Joined Mar 31, 2012
26,398
I think a much more sensible progression would be an RS flip flop, a gated version and finally the D version.

I wouldn't call the final product "clocked" either. Maybe general parlance has changed, but that used to be a "gated latch."
I agree -- but this author chose a different route. Maybe a good one, maybe a bad one, but their choice to make. It's more troubling (to me) that they would seem to have fumbled the ball using their chosen approach, but that may truly be simply a silly mistake like we all make. But it could also be that this is a case of the blind leading the blind, which is all-too-common, especially in works with words like "practical" and "for inventors" in the title. Often these are written by people who, themselves, do not have a firm foundation in the fundamentals and have decided to help others that have as poor a grasp as they do -- the intentions are usually commendable, but the execution is often lacking.
 
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