There are three models of each of 74HC74, 74HCT74 and 4013 on my copy of SPICE. Are these likely to be "behavioral" models or simulations of the actual circuit inside the device? (How would I tell?) Some of them have a .i suffix - does that mean anything?
I'm simulating a circuit where the voltage on the D-input is a far-from-ideal logic signal. How likely is it that I would get realistic results?

 

Some of them have a .i suffix - does that mean anything?

AFAIK that suffix indicates an International version of the symbol, but doesn't affect function. Can't answer your other questions.

 

I believe most (if not all) of standard-logic models in Spice are behavioral, so they generally give a good approximation of the gate operation for normal digital signals, but may not otherwise.

Regardless of that, the D input is clocked so will respond to that voltage depending upon whether it's above or below the the D input logic threshold when the clock transitions.

In a real circuit, there is a possible problem, called metastability, where the output may take a long time to respond if the input is at the logic-threshold when the clock transitions, which would not be shown in a simulation.

What is the nature of your D signal?

A slowing varying signal can be put through a gate with a Schmitt-trigger input to square it up and minimize possible problems around the logic trip level.

 

What is the nature of your D signal?

A slowing varying signal can be put through a gate with a Schmitt-trigger input to square it up and minimize possible problems around the logic trip level.

It's a delta-sigma modulator, and the D input is the output of the integrator. I originally had a comparator. The threshold of the comparator is arbitrary as the feedback from output to input eliminates any errors due to it, so I wondered how well it would work without the comparator.
Answer - no different.
But then I thought - this isn't a real D-flip-flop, it's a behavioural D flip-flop, with infinite gain on the input at a certain threshold, so no metastable states etc.
My usual response would be to build it and find out, but that gives me the answer for one randomly selected 74HC74, (whereas SPICE gives me the answer for a perfectly average 74HC74).
The one thing that made a mess of it was adding hysteresis!

 

There are three models of each of 74HC74, 74HCT74 and 4013 on my copy of SPICE. Are these likely to be "behavioral" models or simulations of the actual circuit inside the device? (How would I tell?) Some of them have a .i suffix - does that mean anything?
I'm simulating a circuit where the voltage on the D-input is a far-from-ideal logic signal. How likely is it that I would get realistic results?

HI

Yes. Those are all "behavioral" model libraries originally created by the late Helmut SenneWald of LTspice group fame. They are simple models and mostly only include prop delay timings. Some include setup/hold timings. The input and output buffers do have a timing curve that changes based on Supply voltage.

I've added many models that use those libraries.
Perhaps I can help....what do you need?

 

Yes. Those are all "behavioral" model libraries originally created by the late Helmut SenneWald of LTspice group fame. They are simple models and mostly only include prop delay timings. Some include setup/hold timings. The input and output buffers do have a timing curve that changes based on Supply voltage.

I'm a bit skeptical that every DFF model for every simulator that uses any SPICE variant were all created by one person.

I could easily believe that the original model files for the libraries distributed by a particular simulator, such as LTspice, were created by one person, but I have a really hard time believing that every component manufacturer that distributes device libraries for their parts all use the same model files from a single person, especially as the SPICE models have evolved and changed radically over the decades.

 

There are three models of each of 74HC74, 74HCT74 and 4013 on my copy of SPICE. Are these likely to be "behavioral" models or simulations of the actual circuit inside the device? (How would I tell?) Some of them have a .i suffix - does that mean anything?
I'm simulating a circuit where the voltage on the D-input is a far-from-ideal logic signal. How likely is it that I would get realistic results?

Which SPICE are you using?

Where did the models come from? Were they included with the simulator, or obtained elsewhere?

They are almost certainly behavioral, since simulating the actual circuit would be both extremely slow, and expose the actual circuit to prying eyes. Even if the actual circuit were supplied in the subcircuit definition, the simulation results would only be as good as the quality of the transistor models used, and transistor models for modern IC processes are incredibly complex (and, hence, slow).

In general, simulation of transistor-level circuits do not scale well, particularly to the size of circuits involved with digital logic.

As a result, the behavior (no pun intended) of a behavioral circuit is predicated on the assumption that the input/output conditions meet some expectations. If you have a really strange waveform, all bets are pretty much off.

 

I'm a bit skeptical that every DFF model for every simulator that uses any SPICE variant were all created by one person.

I did not write that EVERY library was written by one person. That would be silly.

but I have a really hard time believing that every component manufacturer that distributes device libraries for their parts all use the same model files from a single person, especially as the SPICE models have evolved and changed radically over the decades.

Again...that would be silly.

I was under the impression the model library lan0 is referring to are LTspice libraries, since that is a commonly used simulator here on AAC.

 

i was under the impression the model library lan0 is referring to are LTspice libraries, since that is a commonly used simulator here on AAC.

They are in a directory called zzz so I think they came from @Bordodynov .

I wasn't expecting to find logic models down to the transistor scale for complex logic, but I thought a D-type flipflop modelled at the transistor scale might be a possibility.
Obviously, every manufacturer's 74HC74 may be different inside even if the all appear to do the same job.
(I know that from 4013s, where every manufacturer's 4013 don't behave identically!)

 

They are in a directory called zzz so I think they came from @Bordodynov .

Yes. The libraries you've mentioned originate from LTspice group and are included in Bordodynov's distribution.

I wasn't expecting to find logic models down to the transistor scale for complex logic, but I thought a D-type flipflop modelled at the transistor scale might be a possibility.
Obviously, every manufacturer's 74HC74 may be different inside even if the all appear to do the same job.
(I know that from 4013s, where every manufacturer's 4013 don't behave identically!)

The difficulty is obtaining accurate cmos transistor models to use to build the devices. They seem to be a well guarded IP secret.

 

If in reality a smooth signal is fed to the C input for the 74HC74, then there will be problems. Hysteresis is required. I have made several models of the HEF4000. These are half transistor models - the output is made using transistors. For the HEF4013B I implemented hysteresis for input C.
My advice: in order not to tempt fate, add a buffer with hysteresis. Or use 74lvc1g74 which has hysteresis at the input.

 

Interesting. Yours seems to be the Nexperia (ex Philips) internal circuit. TI's is similar with AND gates, and OnSemi's (ex Motorola) is done entirely with gates (no bilateral switches). Whether that corresponds to real life is anyone's guess! I did a very small amount of IC design work back in the 1980s and that favoured the bilateral switch. I think it is more economic on transistors than complete gates.
I suspect the success or failure would depend on how much gain the front end buffers have (I'm guessing about x50, because that works for a 4069/74HCU04.
Hysteresis doesn't work with the Delta Sigma circuit, but it should be immune from comparator jitter because of the D-latch that follows it.
Looks like I might have to keep the comparator.