D-type Flip Flop using logic gates, LTspice says "timestep too small!"

Thread Starter

MrsssSu

Joined Sep 28, 2021
201
View attachment 270467
View attachment 270468
View attachment 270469
Both pictures are quoted from here and here. I am trying to simulate it in LT Spice using Logic gates as the Level Triggered D Type Flip-flop and this circuit converts f to f/2 that is halving the input frequency.
However, I got the error timestep is too small in LT Spice. May I know how to solve this? Below is my LT Spice file attached.


Thank you for reading and have a nice day:)
 

Attachments

Last edited:

MrChips

Joined Oct 2, 2009
26,511
If two waveforms are of different frequencies they cannot be in sync unless there is an integer ratio between the two frequencies.
 

Papabravo

Joined Feb 24, 2006
18,817
In general, the answer is no. If small adjustments in the frequency of one of the square waves are allowed, then that square wave can be synchronized to a reference frequency that does not change. the circuit is called a PLL (Phase Locked Loop). It takes more than a little bit of circuit and mathematics background to understand what is going on. Digesting it one bit at a time is the way to go on this one.
 

Thread Starter

MrsssSu

Joined Sep 28, 2021
201
1656649819780.png
1656649852486.png
1656650023642.png
Both pictures are quoted from here and here. I am trying to simulate it in LT Spice using Logic gates as the Level Triggered D Type Flip-flop.
However, I got the error timestep is too small in LT Spice. May I know how to solve this? Below is my LT Spice file attached.


Thank you for reading and have a nice day:)
 

Attachments

Ian0

Joined Aug 7, 2020
5,533
I thought you meant a real-life circuit. If you join not-Q to D then it divides by two in real-life, regardless of whether SPICE can or can’t work out what’s going on!
(Leaving this one to the SPICE experts)
 

Thread Starter

MrsssSu

Joined Sep 28, 2021
201
hi mrss
Is this what you are trying to do.???
Your circuit is unstable.

E
Wow. You got it running. Can you attach your LT Spice file ? Hmm, the circuit should halve the input frequency. Not sure why unstable. Do you think i need to give it an initial condition at D? Because without initial condition at D, it will not give any output for the entire logic gate? 1656665495261.png:)
 
Last edited:

Thread Starter

MrsssSu

Joined Sep 28, 2021
201
I thought you meant a real-life circuit. If you join not-Q to D then it divides by two in real-life, regardless of whether SPICE can or can’t work out what’s going on!
(Leaving this one to the SPICE experts)
HI sir, do you mean the circuit will work out in real life although LT Spice simulation will have a hard time figuring out the output signal :)?
 

crutschow

Joined Mar 14, 2008
30,122
However, I got the error timestep is too small in LT Spice.
I played around with those ideal AND gates in LTspice and could not get them to work properly.
There was a gate output changing states, even when one of the inputs was low, which an AND gate should not do.
So that gate model seems to be flakey.
 

Papabravo

Joined Feb 24, 2006
18,817
It might be worthwhile to review the LTspice Help file on the "A" series devices. Getting them to behave as you want is more difficult than you imagine since the default values have a tendency to cause a variety of problems.

A. Special Functions
INV, BUF, AND, OR, and XOR are generic idealized behavioral gates. All gates are netlisted with eight terminals. These gates require no external power. Current is sourced or sunk from the complementary outputs, terminals 6 and 7, and returned through device common, terminal 8. Terminals 1 through 5 are inputs. Unused inputs and outputs are to be connected to terminal 8. The digital device compiler recognizes that as a flag that that terminal is not used and removes it from the simulation. This leads to the potentially confusing situation where AND gates act differently when an input is grounded or at zero volts. If ground is the gate's common, then the grounded input is not at a logic false condition, but simply not part of the simulation. The reason that these gates are implemented like that is that this allows one device to act as 2-, 3-, 4- or 5- input gates with true, inverted, or complementary output with no simulation speed penalty for unused terminals. That is, the AND device acts as 12 different types of AND gates. The gates default to 0V/1V logic with a logic threshold of .5V, no propagation delay, and a 1Ohm output impedance. Output characteristics are set with these instance parameters:

NameDefaultDescription
Vhigh1Logic high level
Vlow0Logic low level
Trise0Rise time
TfallTriseFall time
Tau0Output RC time constant
Cout0Output capacitance
Rout1Output impedance
RhighRoutLogic high level impedance
RlowRoutLogic low level impedance
Note that not all parameters can be specified on the same instance at the same time, e.g., the output characteristics are either a slewing rise time or an RC time constant, not both.

The propagation delay defaults to zero and is set with instance parameter Td. Input hold time is equal to the propagation delay.

The input logic threshold defaults to .5*(Vhigh+Vlow) but can be set with the instance parameter Ref. The hold time is equal to the propagation delay.


The exclusive XOR device has non-standard behavior when more than two inputs are used: The output is true only when exactly one of all inputs is true. Use the associative property of XOR's with multiple XOR devices to implement an XOR block with more than two inputs.

The Schmitt trigger devices have similar output characteristics as the gates. Their trip points are specified with instance parameters Vt and Vh. The low trip point is Vt-Vh and the high trip point is Vt+Vh.

[NB. de Papabravo The default value of Vh is not specified in the Help file but is empirically determined to be 25 mV]

The gates and Schmitt trigger devices supply no timestep information to the simulation engine by default. That is, they don't look when they are about to change state and make sure there's a timestep close to either side of the state change. The instance parameter tripdt can be set to stipulate a maximum timestep size the simulator takes across state changes.

I have highlighted some points that may be relevant to the problem at hand.
 
Last edited:

ci139

Joined Jul 11, 2016
1,862
it's a "digital pass gate (with complementary outputs)" - that transmits at C=HIGH CD4042
D-Flop is a different beast - see SN7474 or 74HC74

many LTspice Digital circuits do not settle before some input or before the SET/RESET is applied

for the RS-Latch as the one formed from the two 2-input NAND-s - resolving the steady start is setting Td or Vt parameters to differ by a tiny but still sufficient amount ←← e.g. - you set the (otherwise not existing) priority for simultaneous input signals

what may affect the "Timestep too small" - is the rise/fall times along with the on-time of the driving signal source . . . a small variation to these may affect if the "timestep" 'error' occurs or how fast it occurs
 

Bordodynov

Joined May 20, 2015
2,995
I am surprised at the ignorance. But ignorance is not a vice, of course, if one seeks to increase one's knowledge.
A single-cycle D-trigger cannot be a divider. You need a push-pull. When I designed CMOS circuits for clocks I used dynamic frequency dividers on 9 transistors. I used 4 to 5 of them on the input. This saved space and current consumption of the chip. With these and an improved quartz oscillator I got a chip consumption current of 125 nA. It is an average value for 500 chip samples.

View attachment 270532
 

Attachments

Top