Constant Current of 100-600uA over Dynamic 1k-100k load

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Thread Starter

danielantonic

Joined Sep 22, 2019
62
Hello all

I'm trying to simulate a constant current circuit that will provide 100-600uA over a dynamic 1k-100k ohm load (which would mean a 60V source voltage). I've been playing with an OP Amp/MOSFET design in the circuit simulator from https://www.falstad.com. The pot and 10k simulate the dynamic load, the voltage feeding the 800k resistor is to simulate a 0-5V signal from a DAC. I think I have the correct values for the resistors now, but can someone confirm I am on the right track please? If possible, could someone shed light on the relevant math to figure out the resistor values (other than ohm's law ;-) )
Thank you in advance!

1639919651931.png

PS: Here is the code if anyone wants to have a look at it at falstad.com:


$ 1 0.000005 11.558428452718767 50 10 50 5e-11
f 384 208 432 208 0 0.1 0.02
w 352 32 352 48 1
g 432 432 432 464 0 0
R 352 32 352 0 0 0 40 60 0 0 0.5
a 192 208 288 208 9 15 -15 1000000 0.0005216453928277795 0.0005249343832020998 100000
r 432 304 432 432 0 1
r 384 208 288 208 0 10000
r 352 304 272 304 0 1000
w 192 224 192 304 0
w 352 304 432 304 0
w 432 304 432 224 0
w 192 304 272 304 0
w 432 144 432 192 0
174 352 48 400 144 1 90000 0.9851000000000001 LOAD
w 400 96 416 96 0
w 416 96 432 96 0
172 112 96 64 96 0 7 4.2 5 0 0 0.5 Voltage
r 144 96 144 192 0 800000
r 144 208 144 288 0 100
w 112 96 144 96 0
w 144 192 192 192 0
w 144 192 144 208 0
g 144 288 144 320 0 0
r 432 96 432 144 0 10000
 

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dl324

Joined Mar 30, 2015
14,686
What are the part numbers for the opamp and MOSFET? What are the opamp supply voltages?

The 10k resistor on the gate of the MOSFET can be much smaller. It's just there to prevent oscillations from driving a capacitive load. The 1k resistor on the inverting input isn't necessary.

Is the 4.2V a stable voltage source? An 800k (not a standard value) with 1% tolerance could have a resistance of 792-808k. That range swamps your 100 ohm resistor. I'd use a low voltage zener with a pot to vary current.

With such low currents, you're going to need to null the offset voltage of the opamp.
 

Alec_t

Joined Sep 17, 2013
12,890
The FET source resistor needs to be bigger. Try 7.5k. That will give your load 600μA when the DAC voltage is 4.5V.
 

crutschow

Joined Mar 14, 2008
30,102
The FET source resistor needs to be bigger. Try 7.5k. That will give your load 600μA when the DAC voltage is 4.5V.
As Alec noted, you need more voltage across the source resistor to minimize the effects of the op amp input offset voltage.
 
Last edited:

Irving

Joined Jan 30, 2016
2,769
Here's one that works. As said above, a bigger source (current sense) resistor overcomes a number of issues - MOSFET non-linearity, op-amp input offset voltage and bias, etc. So a general purpose op-amp and a common MOSFET will work well. You need a bit more compliance volts, eg 70v, again to avoid non-linearity.

V3 generates a 1 - 6v current selection, ie 1v per 100uA. V4 is a simple technique for creating a time-stepped resistor, by time-stepping a voltage across a known resistor and using that to control the value of a resistor (R2). Both the drive voltage and the resistor value are shown in plot 1.

Plot 2 shows the feedback voltage from the current sense resistor R1 and the gate drive voltage. Unless you plan on having fast transient current steps you don't need anything more complicated here. The opamp slew rate, output current capability and the MOSFET gate charge limit this to about 60uA/mS; faster transitions need a better opamp, a faster MOSFET and possibly a more complex feedback arrangement. Plot 3 shows the drain (constant) current and the compliance voltage at the drain of M1.

1639934242926.png

Netlist:

M1 d g fb fb IRL530NS_L
XU1 drv fb +15 0 g OP777
R1 fb 0 10k
R2 N001 d R=V(Vres)
V1 N001 0 70
V2 +15 0 15
V3 drv 0 PULSE(1 6 0 50m 50m 5m 110m)
V4 vres 0 PWL(0 1k 107m 1k 109m 10k 217m 10k 219m 100k 330m 100k)
R3 vres 0 1
.model NMOS NMOS
.lib ..\LTspiceXVII\lib\cmp\standard.mos
* 10k gives 1V - 6V for 100 - 600uA
.tran 0 330m 0
.lib ADI.lib
.backanno
.end
 
Last edited:

Thread Starter

danielantonic

Joined Sep 22, 2019
62
Here's one that works. As said above, a bigger source (current sense) resistor overcomes a number of issues - MOSFET non-linearity, op-amp input offset voltage and bias, etc. So a general purpose op-amp and a common MOSFET will work well. You need a bit more compliance volts, eg 70v, again to avoid non-linearity.

V3 generates a 1 - 6v current selection, ie 1v per 100uA. V4 is a simple technique for creating a time-stepped resistor, by time-stepping a voltage across a known resistor and using that to control the value of a resistor (R2). Both the drive voltage and the resistor value are shown in plot 1.

Plot 2 shows the feedback voltage from the current sense resistor R1 and the gate drive voltage. Unless you plan on having fast transient current steps you don't need anything more complicated here. The opamp slew rate, output current capability and the MOSFET gate charge limit this to about 60uA/mS; faster transitions need a better opamp, a faster MOSFET and possibly a more complex feedback arrangement. Plot 3 shows the drain (constant) current and the compliance voltage at the drain of M1.

View attachment 255529

Netlist:

M1 d g fb fb IRL530NS_L
XU1 drv fb +15 0 g OP777
R1 fb 0 10k
R2 N001 d R=V(Vres)
V1 N001 0 70
V2 +15 0 15
V3 drv 0 PULSE(1 6 0 50m 50m 5m 110m)
V4 vres 0 PWL(0 1k 107m 1k 109m 10k 217m 10k 219m 100k 330m 100k)
R3 vres 0 1
.model NMOS NMOS
.lib ..\LTspiceXVII\lib\cmp\standard.mos
* 10k gives 1V - 6V for 100 - 600uA
.tran 0 330m 0
.lib ADI.lib
.backanno
.end
You ripper! The 10k works perfectly! Thank you so much!!!
 

Thread Starter

danielantonic

Joined Sep 22, 2019
62
Ok, I've moved onto the next step in my simulation - making the constant current bi-directional and controllable by an MCU.

To simulate this I have a voltage divider to drop the 60V to 5V, a DAC to control the current, a switch between 5V and ground to simulate logic levels from an MCU, and a second switch to change the direction of the current flow. In the middle of the H Bridge is a Pot/Resistor to simulate the load.

Other than those parts, does anyone have suggestions on simplifying/streamlining the design?
1639992444517.png
 

crutschow

Joined Mar 14, 2008
30,102
You have the analog current control signal connected to the digital transistor switch control.
How is that supposed to work?

Also you need change the gate resistor values so the gate-source voltage is no more than about 10V when the MOSFET is on, otherwise you may zap the gate.
 
Last edited:

Irving

Joined Jan 30, 2016
2,769
You can't sensibly drop 60v to 5v for a real MCU like that. You need a proper voltage regulator or, better, a buck converter. Depending on how you generate the 60v, you may find you have other more appropriate voltages in the system to work from.

Your P-channel MOSFETs will die when you turn them on, as the gate voltage will rise (actually fall) more than 15v relative to its source.

Your DAC output gating plus P-channel control won't be reliable.. if it works at all...

What's the long-term goal for this circuit?
 
Last edited:
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