Okay, a few things that need clarification:

How did you determine the capacitance values? Did you just play around with it or did you calculate it?

Bucketbrigade seems to have 100f? Isn't that too big?

Lower case "f" indicates femptofarads, i.e., 1e-15 farads or 0.1pF. I just started out with that value, and it seemed to work.

Then, what does the E1, E2 and E3 do?

The E element is a voltage controlled voltage source, which is an ideal amplifier with infinite input impedance, zero output impedance, infinite bandwidth, and gain specified by the value. E1 and E2 are op amps configured as voltage followers. It would have been simpler had I set the gains to 1, and grounded the -inputs. They are the gain elements of a 4 pole active Bessel filter. E3 is an amplifier with a gain of 10.

Third, why put in a source follower?

The source follower provides a low output impedance to drive the sample and hold, isolating the 1pF hold capacitor from the 0.1pF "bucket" in the last stage.

I believe after some stages, the signal will go down, so i will need an amplifier to boost the signal up?

I don't know. You may not have noticed that my BB circuit actually had gain of about 1.1 (Vout in the waveform window had to be scaled down by 0.900 to get the output amplitude to the same amplitude as the input). I don't know why.

Also, the Vcc setup in the middle, i assume that is the global setting, right?

Thanks.

All nodes labeled vcc are connected to the positive side of V4.

Attached are the dimensions of all the transistors, except for M9-M11. M9-M11 are each scaled to be ten devices in parallel, relative to the size of the others. These dimensions I picked rather arbitrarily. They were not optimized, even for this circuit, and certainly not for whatever fab process you will be using. You need to be using models that come from your fab process, and probably a more sophisticated simulator, if you really expect your design to work in hardware.
You have a lot of work to do.
You might want to rethink doing it digitally.
If this is homework, I've probably helped you more that I should have. I hope you can show your working design, and don't actually have to produce hardware.

 

Well, i actually have to simulate it first, work out the parameters and then if it can fit on the size of die that i have, then it goes for fabrication. Right now the idea is to get it working in Simulation first.

I am using the Cadence Virtuoso CAD suite, and it's for 0.35micron process, but the space i have been allotted is not much. So i have to actually see i can even put capacitors in there or maybe just use the Gate capacitance of the Nmos.

I will put up my design soon.

Thanks for your help, RonH.

 

Well, i actually have to simulate it first, work out the parameters and then if it can fit on the size of die that i have, then it goes for fabrication. Right now the idea is to get it working in Simulation first.

I am using the Cadence Virtuoso CAD suite, and it's for 0.35micron process, but the space i have been allotted is not much. So i have to actually see i can even put capacitors in there or maybe just use the Gate capacitance of the Nmos.

I will put up my design soon.

Thanks for your help, RonH.

You'll have to scale your devices to fit the process.

 

You'll have to scale your devices to fit the process.

Hi Ron H,

I was busy with my exams and other stuff, but now am working on this project.

May i ask if you know any resources where i can read more about bucket brigade and their real time implementation?

Like any documentation, books or online sources?

I have tried IEEExplore, but it only gives the original papers by Allan Sangster as he made the concept in the 70s.

I need to know this, as i have to present this, and i want to do my history and background check on it.


Thanks.

 

Hi Everyone,

As i posted to Ron H above, anyone of you, if you know about good resources to read up on the bucket-brigade delay line, please let me know.

Thanks.

 

*bump* -Anyone?

 

Have you tried to Google?: bucket brigade delay line

Ken

 

Hello,

Have a look at the attached scanned data sheet of the old TDA1022.

Bertus

 

Hello,

Have a look at the attached scanned data sheet of the old TDA1022.

Bertus

Thanks Bertus!

 

Have you tried to Google?: bucket brigade delay line

Ken

Hi,

Yes i tried to google, but the only results i got were the papers published by Allan Sangster and his team in the 1960-70s.

I was wondering if there is any analog design book that can be of help.

Thanks.

 

Going back to Ron H's attached diagrams,

Shouldn't the source of the NMOS be connected to the ground or the same potential as the substrate?

Also, if i am correct in deducing, the Drain of M1 is connected to the source of M2???

Second,

the action potential shows the graph for Volts. What if i tried micro or milli volts?

 

Going back to Ron H's attached diagrams,

Shouldn't the source of the NMOS be connected to the ground or the same potential as the substrate?

Why would you think that?

Also, if i am correct in deducing, the Drain of M1 is connected to the source of M2???

MOSFETs are symmetrical. The drain and source are interchangeable.

Second,

the action potential shows the graph for Volts. What if i tried micro or milli volts?

What if you did? What if you learned LTspice and tried it yourself?

Are you trying to build hardware?

 

Why would you think that?

MOSFETs are symmetrical. The drain and source are interchangeable.

What if you did? What if you learned LTspice and tried it yourself?

Are you trying to build hardware?

Wait......is this still valid for CMOS which is what i am using?

I am using Cadence, and yes it will be built into hardware.

From what i have read, source and substrate on the NMOS are kept at the same potential, usually ground, and gate and and drain voltages are varied.

I would appreciate if you could briefly explain otherwise.

 

Wait......is this still valid for CMOS which is what i am using?

I am using Cadence, and yes it will be built into hardware.

From what i have read, source and substrate on the NMOS are kept at the same potential, usually ground, and gate and and drain voltages are varied.

I would appreciate if you could briefly explain otherwise.

Those rules are for logic circuits. This is analog. Different rules. The circuit I drew is not CMOS, it is NMOS. You will probably use CMOS logic to generate the clock pulses.

 

Those rules are for logic circuits. This is analog. Different rules. The circuit I drew is not CMOS, it is NMOS. You will probably use CMOS logic to generate the clock pulses.

hmm.....

Well, yes i am using NMOS for time being, and if the simulation shows slight bit of delay, it is something.

I am using simple pulse generator in cadence, as VPulse to generate clock,
I am simply defining the voltage and the period as the parameter.

What voltage do you think is appropriate so that the Gate channel opens properly?

Secondly, should i continue to wire my NMOS drain to source and putting the input signal to be delayed, i.e. Action potential, at the source? and measure the delay at the drain node?

 

The reason you aren't finding long analog delay lines is that digital is much easier to work with, and you are at the silicon level anyway.

Even when Bucket Brigade delays were around, analog delay lines, such as quartz and acoustic waves through paths were used, since they worked better.

Digital delays work better than the physical analog delays, and aren't fragile. 1ms is a long delay in silicon.

Another Analog Delay for longer delays was made with a tape loop, a write head, and a read head. Adjust the spacing between the heads to change the delay.

When is your project due? Is this a final project of some sort? How many attempts do you get on the silicon?

 

The reason you aren't finding long analog delay lines is that digital is much easier to work with, and you are at the silicon level anyway.

Even when Bucket Brigade delays were around, analog delay lines, such as quartz and acoustic waves through paths were used, since they worked better.

Digital delays work better than the physical analog delays, and aren't fragile. 1ms is a long delay in silicon.

Another Analog Delay for longer delays was made with a tape loop, a write head, and a read head. Adjust the spacing between the heads to change the delay.

When is your project due? Is this a final project of some sort? How many attempts do you get on the silicon?

Thanks for your reply.

I cannot do digital implementation as in my case it will consume too much power. Basically, i have to implement an analog delay line on a die which will incorporate other analog systems as well, like 5 transistor amplifiers etc.

The full die size is 2mmX2mm, divide that by about 100 and that is the space i have been allotted to implement the analog delay.

As you can see from Ron H's attachments on page 4 of this thread, the concept seems to work in simulation. So my only question right now is concerning the wiring of the NMOS. If i can get even fraction of the 1ms delay, it is something, because ultimately, the number of buckets i can implement in the bucket brigade and their capacitors, is dependent on the space i have, plus the 0.35micron process we will be using for fabrication.



My project is due in 3 weeks.

 

hmm.....

Well, yes i am using NMOS for time being, and if the simulation shows slight bit of delay, it is something.

I am using simple pulse generator in cadence, as VPulse to generate clock,
I am simply defining the voltage and the period as the parameter.

What voltage do you think is appropriate so that the Gate channel opens properly?

That is probably process dependent, and input DC level dependent.

Secondly, should i continue to wire my NMOS drain to source and putting the input signal to be delayed, i.e. Action potential, at the source? and measure the delay at the drain node?

As I said, source and drain are interchangeable. A MOSFET that is physically and chemically (doping) symmetrical will work the same in either direction. In the bucket brigade, and other circuits, such as analog switches, source and drain are irrelevant. If you really want to define them, then in an NMOS, the drain is the terminal that is more positive than the other terminal, which will be the source. When the voltage polarity between the terminals reverses, the definitions of the terminals reverses.
Are you sufficiently confused? That is not my intention, but I know it may be confusing.

 

That is probably process dependent, and input DC level dependent.

As I said, source and drain are interchangeable. A MOSFET that is physically and chemically (doping) symmetrical will work the same in either direction. In the bucket brigade, and other circuits, such as analog switches, source and drain are irrelevant. If you really want to define them, then in an NMOS, the drain is the terminal that is more positive than the other terminal, which will be the source. When the voltage polarity between the terminals reverses, the definitions of the terminals reverses.
Are you sufficiently confused? That is not my intention, but I know it may be confusing.

Oh thanks, yes it clears up now.

The reason why i was wondering if Source and Drain are not interchangeable is because most textbooks fail to make this deduction.

So in my case, i use the Clock to open the gates, while the input signal gets in at either drain or source and then the output delay (hopefully) is measured at the drain or source, right?

 

Ron H,

Going back to your schematic, you show transistor dimensions.

Width is 5u
Length is 100u
Drain and Source as 240u.

Aren't these too big of a figures for the 0.35u process i am using?

Please answer these questions and the ones in the above post.

Thank you.