The below is an idea, I haven't try it yet, it might need some modification.

Signal → CD4066 In → Control pin → CD4066 Out → Signal delay for 1mS
Signal → Voltage comparator (> -7V) → negtive Voltage cut off circuit → 0.01uf → Ne555 mono 1mS Delay → NPN Transistor inverter → CD4066 control pin

The Power for CD4066 and Op Amp should be ≧ +7.5V,0,-7.5V.
Negtive Voltage cut off circuit, it will cut off the negtive voltage to protecting the NE555, the voltage only from 0 to +V.
The power of NE555 Only just need 0,+V.
Voltage comparator - ex: LM339,LM393 or Op amp As LM358, LM324.
CD4066 Control pin will actived by high.

 

The below is an idea, I haven't try it yet, it might need some modification.

Signal → CD4066 In → Control pin → CD4066 Out → Signal delay for 1mS
Signal → Voltage comparator (> -7V) → negtive Voltage cut off circuit → 0.01uf → Ne555 mono 1mS Delay → NPN Transistor inverter → CD4066 control pin

The Power for CD4066 and Op Amp should be ≧ +7.5V,0,-7.5V.
Negtive Voltage cut off circuit, it will cut off the negtive voltage to protecting the NE555, the voltage only from 0 to +V.
The power of NE555 Only just need 0,+V.
Voltage comparator - ex: LM339,LM393 or Op amp As LM358, LM324.
CD4066 Control pin will actived by high.

How is that going to sample the signal at 50kHz and create a 5mS delay of the sampled signal?
http://forum.allaboutcircuits.com/showpost.php?p=550912&postcount=4

 

How is that going to sample the signal at 50kHz and create a 5mS delay of the sampled signal?
http://forum.allaboutcircuits.com/showpost.php?p=550912&postcount=4

Maybe the OP needs to draws the wave form to shows that how the relationship of sample rate with 1 mS delay.

 

Maybe the OP needs to draws the wave form to shows that how the relationship of sample rate with 1 mS delay.

His description is fine. Either delay an analog signal by 1ms (not 1 milliseimen, as everyone keeps insisting) and then sample it at 50kHz, or sample a signal at 50kHz and then delay the result of that by 1ms. Either way would work, the latter being the more likely approach in practice.

 

His description is fine. Either delay an analog signal by 1ms (not 1 milliseimen, as everyone keeps insisting) and then sample it at 50kHz, or sample a signal at 50kHz and then delay the result of that by 1ms. Either way would work, the latter being the more likely approach in practice.

I'm not care about the sample rate, because it is a long story, so, I only focus on 1mS delay, the idea may work or not work, but the delay circuit is separate from sample circuit.

 

So it gets back to Ron H's question. How is your circuit going to result in a specific amount of delay? In particular, if, at t=3.450s, the voltage at the input is 1.23V and, at 3.451s it is 2.19V, how will your circuit result in the voltage at the output being 1.23V at t=3.451s and 2.19V at 3.452s?

 

At the OP: Have you looked at just using an RC delay? You can implement in on the IC using a switched-capacitor filter to make it adjustable.

 

So it gets back to Ron H's question. How is your circuit going to result in a specific amount of delay? In particular, if, at t=3.450s, the voltage at the input is 1.23V and, at 3.451s it is 2.19V, how will your circuit result in the voltage at the output being 1.23V at t=3.451s and 2.19V at 3.452s?

Thanks, I know what you mean.
I forgot the timing that when the control pin is on, the signal on the output pin is not start from the begining, it's different from rc delay.
Usually we will use rc delay, if the phase can be ignore, maybe that is a easy way.

 

Okay thanks for the replies guys.

I am even more confused now.

in 1970s F.Sangster came up with the bucket-brigate aproach. Can i not implment that using simple Nmos or Pmos?

 

The below is an idea, I haven't try it yet, it might need some modification.

Signal → CD4066 In → Control pin → CD4066 Out → Signal delay for 1mS
Signal → Voltage comparator (> -7V) → negtive Voltage cut off circuit → 0.01uf → Ne555 mono 1mS Delay → NPN Transistor inverter → CD4066 control pin

The Power for CD4066 and Op Amp should be ≧ +7.5V,0,-7.5V.
Negtive Voltage cut off circuit, it will cut off the negtive voltage to protecting the NE555, the voltage only from 0 to +V.
The power of NE555 Only just need 0,+V.
Voltage comparator - ex: LM339,LM393 or Op amp As LM358, LM324.
CD4066 Control pin will actived by high.

ScottWang,

Can you please explain it a bit more?
Thanks.

 

At the OP: Have you looked at just using an RC delay? You can implement in on the IC using a switched-capacitor filter to make it adjustable.

Wouldn't the RC filter increase the distortion?

 

I created a simulation of a simple BBD. It would require a lot of massaging, and simulation with a real chip-level simulator optimized for MOS circuitry and models.
I also created a PWL file with a Bessel filter to recreate your input waveform.
The MOSFETs were just created with seat-of-the pants geometry. You can descend into the NMOS symbols to see the parameters.
There are more sophisticated topologies. I took this one from BUCKET BRIGADE DEVICES - CIRCA 1976 by Buss and Weckler.
Be aware that I have never designed or worked on a BBD device. The closest I came was dynamic RAM chip design, about 14 years ago. My point is, I won't be able to take this much farther than what you see in the attachment.

 

Okay thanks for the replies guys.

I am even more confused now.

in 1970s F.Sangster came up with the bucket-brigate aproach. Can i not implment that using simple Nmos or Pmos?

You can only implement an approximation. A bucket-brigade device uses a single channel having multiple gates over it. Think of a garden hose in which you can move a chunk of water from one end to the other by squeezing the hose closed on both sides of the packet of water and then sliding your hands along the hose forcing the water to move along in sync with that. Now imagine a bunch of people standing at fixed points along the hose with the hands overlapped so that every inch (or microinch) of the hose can be squeezed shut by someone. Now imagine that one third of the hands (evenly spaced) are "open" and that each of those sections contain water (some more than others). Now imagine that the hands on the section next to each of these (in the direction of intended flow) opens up making the section twice as big. Now the original section closes reducing the open section to the original size, but it has moved one hand toward the eventual end.

What's important is that all of the water that was in the original section gets pushed into the new section. That's where the overlapping gates come in. If you can't have overlapping gates but, rather, individual transistors, the you can't push all of the charge along -- some of it will get left on the unavoidable parasitic capacitances between the two transistors, principally those associated with the source-drain implants.

 

ScottWang,

Can you please explain it a bit more?
Thanks.

Ron H and WBahn already pointed out the delay is too short, this idea didn't suit your need, so what do you want to know or which part that you don't understand, if you try to draw the circuit, maybe you will find more or where that you don't get it.

 

Wouldn't the RC filter increase the distortion?

Yes, but so will everything else being discussed. The issue is whether the amount of distortion a given technique results in is acceptable.

 

I created a simulation of a simple BBD. It would require a lot of massaging, and simulation with a real chip-level simulator optimized for MOS circuitry and models.
I also created a PWL file with a Bessel filter to recreate your input waveform.
The MOSFETs were just created with seat-of-the pants geometry. You can descend into the NMOS symbols to see the parameters.
There are more sophisticated topologies. I took this one from BUCKET BRIGADE DEVICES - CIRCA 1976 by Buss and Weckler.
Be aware that I have never designed or worked on a BBD device. The closest I came was dynamic RAM chip design, about 14 years ago. My point is, I won't be able to take this much farther than what you see in the attachment.

Thanks Ron, I had been simulating a similar setup.

What CAD suite are you using? and i see you are getting a delay, albeit a short one. I am using Cadence Virtuoso.

I will post mines soon, what is the best way to post pictures here, guys?


Thanks for all the useful replies.

 

I created a simulation of a simple BBD. It would require a lot of massaging, and simulation with a real chip-level simulator optimized for MOS circuitry and models.
I also created a PWL file with a Bessel filter to recreate your input waveform.
The MOSFETs were just created with seat-of-the pants geometry. You can descend into the NMOS symbols to see the parameters.
There are more sophisticated topologies. I took this one from BUCKET BRIGADE DEVICES - CIRCA 1976 by Buss and Weckler.
Be aware that I have never designed or worked on a BBD device. The closest I came was dynamic RAM chip design, about 14 years ago. My point is, I won't be able to take this much farther than what you see in the attachment.

RONH,

Can you explain a bit more the circuit you have on the botton left and the top right?

I see the two top pulse are the clocks connected to the gate of the enhancement mode NMOS. But please explain what the rest are doing, because i don't have those in my design.

Thanks.

 

See the attached annotated schematic for explanations of the blocks.
The delay is short because I only have about 10 stages of delay. A longer bucket brigade will obviously give you more delay.

I'm using LTspice. If you want to try it, I attached the .asc file in my previous post. This needs to be copied into the main LTspiceIV folder. You will also need the action potential.txt file that I posted. Depending on where you put it, you may have to change the location in this line of the PWL voltage source:

PWL repeat forever file="C:\Program Files (x86)\LTC\LTspiceIV\lib\PWL_files\action potential.txt" endrepeat

 

See the attached annotated schematic for explanations of the blocks.
The delay is short because I only have about 10 stages of delay. A longer bucket brigade will obviously give you more delay.

I'm using LTspice. If you want to try it, I attached the .asc file in my previous post. This needs to be copied into the main LTspiceIV folder. You will also need the action potential.txt file that I posted. Depending on where you put it, you may have to change the location in this line of the PWL voltage source:

PWL repeat forever file="C:\Program Files (x86)\LTC\LTspiceIV\lib\PWL_files\action potential.txt" endrepeat

Okay, thanks.

How can i post the image of my schematic? Like should i upload it on Imageshack and then post the link here?

 

See the attached annotated schematic for explanations of the blocks.
The delay is short because I only have about 10 stages of delay. A longer bucket brigade will obviously give you more delay.

I'm using LTspice. If you want to try it, I attached the .asc file in my previous post. This needs to be copied into the main LTspiceIV folder. You will also need the action potential.txt file that I posted. Depending on where you put it, you may have to change the location in this line of the PWL voltage source:

PWL repeat forever file="C:\Program Files (x86)\LTC\LTspiceIV\lib\PWL_files\action potential.txt" endrepeat

Okay, a few things that need clarification:

How did you determine the capacitance values? Did you just play around with it or did you calculate it?

Bucketbrigade seems to have 100f? Isn't that too big?

Then, what does the E1, E2 and E3 do?

Third, why put in a source follower?

I believe after some stages, the signal will go down, so i will need an amplifier to boost the signal up?

Also, the Vcc setup in the middle, i assume that is the global setting, right?

Thanks.