I have some queries regarding capacitor charging using inductively generated HV pulses, in contrast to regular DC.

My understanding is that if the energy supplied by the battery U = QV then the capacitor will always receive and store 1/2 QV (= 1/2 CV^2) due to resistive, inductive and radiative losses.



So with a known value of capacitor being charged from a voltage Vmin to Vmax, as seen on a scope trace and drawn here, one can calculate the energy stored and compare it to what was delivered by the battery and this will be fairly precisely 50%.

If the capacitor is then discharged, whatever energy was stored will again incur a 50% loss such that, over a complete charge-discharge cycle, only 25% of the original energy supplied by the battery is available for whatever the discharge energy might be used for.

Looking now at the situation with HV pulses, of the sort produced from the field collapse of a coil (flyback pulses), as in the circuit below, then I understand that, apart from the voltage dependent switch, this is basically a Boost Converter. As such the energy stored in the coil’s magnetic field is very efficiently transferred to the capacitor with an efficiency of let’s say 95%. The high-intensity discharges are simply to enable the reset of the capacitor so that a train of charging curves can be seen and measured.





My query is that since the above equation (0.5 CV2) for regular DC charging is clearly not applicable here, is there some other way I can theoretically calculate the energy stored in the capacitor or, if that is not possible, then is the best way to discharge the cap through an electronic load to record the energy dissipated and then to apply the 50% loss factor for conventional discharge? This can be done as shown below, but I would like to be able to compare theory with practice.

Thanks

 

one can calculate the energy stored and compare it to what was delivered by the battery and this will be fairly precisely 50%.

No. The energy supplied by the battery will be the same as the energy stored in the capacitor (unless there are resistive losses somewhere).

 

No. The energy supplied by the battery will be the same as the energy stored in the capacitor (unless there are resistive losses somewhere).

No, he is correct. Half the energy is lost if the only current limiting is due to resistance. This is why we use inductors in DC to DC converters. Nothing new here.

 

The 50% energy loss comes from charging or discharging through a resistor.
Using an inductor, such as in the flyback circuit you are using, can theoretically transfer close to 100% of the energy into the capacitor.

And if you use an inductor at in series with the capacitor output to the battery, 100% of the energy can also be transferred from the capacitor to the battery.
Without the inductor, the efficiency drops closer to 50%.

 

Half the energy is lost if the only current limiting is due to resistance.

Agreed, but there was no mention of a resistor in the original post.

 

Agreed, but there was no mention of a resistor in the original post.

In the real world, there is always a resistor, actually, several.

 

I proposed an electronic load or a battery, both of which have resistance, the former definitely so I would suggest. So if the capacitor is discharged into some form of load then is it always 50% that is lost and if not how can one work out or measure the loss during the discharge?

 

To give a bit more meat to the previous suggestion, in the past I have used an electronic load to discharge a capacitor (same 53mF size) and read the direct Wh from the device. This is shown in the pic below that I included in the original post.



In this case, 61.2J has been expended, so is it accurate to say that the capacitor actually held 62.1/0.5 = 124.2J, to start with, assuming a 50% resistive loss?

If that is not a fair assessment then would I need to find out the resistance used in the electronic load and do some form of loss calculation to derive a more accurate value for the % loss?

 

I have used an electronic load to discharge a capacitor

In this case, 61.2J has been expended, so is it accurate to say that the capacitor actually held 62.1/0.5 = 124.2J, to start with, assuming a 50% resistive loss?

No.
If you discharge the capacitor through a resistor to ground, then all the energy in the capacitor between those two voltages is dissipated in the resistor.
You are confusing the loss when charging a capacitor with loss in discharging it (which there isn't).

The 50% loss is when you are charging the capacitor from a voltage source.
The energy provided by the voltage source is twice the energy stored in the capacitor.
But all that energy is dissipated when the capacitor is discharged through a resistor to ground.

 

Ok, that makes life easier. So my electronic load reading is correct.

Do you think then that a simulation of the pulse charging process would accurately allow the calculation of the high transfer efficiency of the battery to the capacitor, or does LTSpice, for example, make too many assumptions or estimates of component behaviours to do that accurately ?

 

Do you think then that a simulation of the pulse charging process would accurately allow the calculation of the high transfer efficiency of the battery to the capacitor, or does LTSpice, for example, make too many assumptions or estimates of component behaviours to do that accurately ?

LTspice is only as good as the device models.
So if you have good models for all the components then LTspice will give a good accuracy of the charging efficiency.

 

Yes that makes good sense but how can one ensure good third-party models except by comparing them with practical data? Seems a chicken and egg situation.

 

In the real world, there is always a resistor, actually, several.

Hi,

If you are referring to the inductor and capacitor ESR and some parallel resistances, then yes, that's true. But in a theoretical discussion we often ignore that in order to understand the more basic operation of the circuits. That allows us to state that an ideal inductor and ideal capacitor can resonate forever after being supplied with even the tiniest of energy.
When we want to get practical, and then and only then, we start to introduce ESR and other resistances and radiation and all that blah blah blah stuff. However, then we can introduce them one by one so we can analyze and better understand the effect of each one individually. That allows us to assess each one by itself and then allows us to combine them when we want to get the entire picture. This helps get a clearer picture of what we might have to upgrade to reach some target efficiency like 90 percent.

 

Yes that makes good sense but how can one ensure good third-party models except by comparing them with practical data? Seems a chicken and egg situation.

In power circuits you always have to bench test, and also life test. There's no way around this. You use the best models you can find to estimate the behavior, then move to a prototype and fully test it. This is the way it has been for years and years. Once you validate a given design, then you can move to production where you might just life test each unit or just life test every so many or pick the units to test randomly in order to monitor the process for units as time goes on and more and more go out the door.

As to the difference in charging, an ideal inductor and ideal capacitor can oscillate indefinitely when supplied with even a little energy. They transfer the energy back and forth over and over again with no losses. It's only when we acknowledge the resistances that we will see the oscillations cease after some time period without the application of any additional energy.
In a boost converter this is often controlled over every cycle or sometimes over multiple cycles where the additional energy is supplied a little at a time in order to meet some output specification. The result, because of the resistances, is usually some loss like 10 percent, 15 percent, even 20 percent or more. 75 percent efficiency (25 percent loss) was very acceptable in the 1970's these days it is probably not very acceptable.
We could look at this in more detail, but understanding the ideal LC oscillator is the most basic theory to understanding how the inductor transfers energy to the capacitor with less loss than when using a resistor. Another view though comes from some basic switching theory (or PWM theory). If you pulse a resistance at a fractional duty cycle D, the apparent resistance goes up by 1/D. A simple example is a 10 Ohm resistor pulsed at 50 percent duty cycle (fractional 0.5) will look like a resistance of 20 Ohms (1/0.5=2, and 2*10=20 Ohms). Pulsed at 25 percent duty cycle (0.25) will look like 40 Ohms. Notice there is no energy conversion there. An inductor and a capacitor can provide true energy conversion from one form to another (20v in, 10v out for example) while PWM alone cannot do that because of that increasing resistance issue.

 

Yes that makes good sense but how can one ensure good third-party models except by comparing them with practical data? Seems a chicken and egg situation.

That's true to a certain extent for models of complex ICs.
But if the circuit just has resistors, capacitors, transistors and diodes (such as shown in your post #1 circuit), then the available models will likely give results within typical engineering tolerances to the real circuit, if you include the parasitic resistances/capacitances for the inductors and capacitors.

 

Notice there is no energy conversion there. An inductor and a capacitor can provide true energy conversion from one form to another (20v in, 10v out for example) while PWM alone cannot do that because of that increasing resistance issue.

Ok, so the losses in pulse charging are due solely to the resistive aspect, as has been discussed, and the duty for the PWM I used is 50%, which will double the apparent resistance, according to your description. So can one calculate the efficiency by just knowing the resistance between the FET Drain and the capacitor and applying some PWM based factor?

 

PRF for the pulses is 50Hz and so if it was 100Hz, it would double the apparent resistance,

The frequency has nothing to do with the "apparent" resistance.

So can one calculate the efficiency by just knowing the resistance between the FET Drain and the capacitor and applying some PWM based factor?

The FET resistance only affects the efficiency of charging the capacitor.
It's unrelated to the efficiency of transferring the capacitor energy to the battery.

 

The frequency has nothing to do with the "apparent" resistance.
The FET resistance only affects the efficiency of charging the capacitor.
It's unrelated to the efficiency of transferring the capacitor energy to the battery.

Sorry, yes I changed it just now to the PWM duty of 50% and took out the frequency. Or are we talking about the effective mark to space ratio of the actual output pulses that are charging the capacitor which is 10uS out of 20mS so 0.0005?

 

Or are we talking about the effective mark to space ratio of the actual output pulses that are charging the capacitor which is 10uS out of 20mS so 0.0005?

The only effect the duty-cycle or the frequency of the PWM has on the efficiency is from the switching losses in the FET, not in it's apparent on-resistance

 

The only effect the duty-cycle or the frequency of the PWM has on the efficiency is from the switching losses in the FET, not in it's apparent on-resistance

Fine, so the apparent resistance that MrAI was talking about is to do with the Drain output pulse that is actually charging the capacitor. If that has a %duty of 0.05% then won’t that make the resistive losses very high thereby significantly offsetting the ‘no loss’ result of the inductance and capacitance?