# bubbled inputs and ouputs

#### alitronic

Joined Jun 13, 2020
47
Hello, when we studied digital electronics we learned that:
Whenever possible, choose gate symbols that so that bubble outputs are connected to bubble inputs, and nonbubble outputs are connected to nonbubble inputs.
Is that due to technical reasons, or simply to good manners in design?
Tnanks

#### BobTPH

Joined Jun 5, 2013
6,293
There is no technical reason for this. I suspect it is just so you can forget about the inversions when designing or analyzing the circuit.

#### DickCappels

Joined Aug 21, 2008
9,615
As BobTPH indicated, generally, the bubble indicates that a particular pin is active high or low. If you connect an active low output to an active high input it will require a person who is interpreting the schematic to go through a more complex analysis.

#### Papabravo

Joined Feb 24, 2006
19,845
It also requires some mental gymnastics to use two different symbols for each type of logic gate. At some point most designers I know decided it would be easier to use the positive logic version rather than the negative logic version.

#### MrChips

Joined Oct 2, 2009
28,127
Hello, when we studied digital electronics we learned that:
Whenever possible, choose gate symbols that so that bubble outputs are connected to bubble inputs, and nonbubble outputs are connected to nonbubble inputs.
Is that due to technical reasons, or simply to good manners in design?
Tnanks
This is a valid question.
The answer is NO.

Firstly, let us understand the basis for this statement.
1) It comes about because every logic gate symbol can be drawn in one of two ways following DeMorgan's Theorem.
2) This only applies to the documentation, i.e. circuit schematics, of the hardware.

What is DeMorgan's Theorem?

Let us take the lowly 7400 quad two input NAND gate.
There are two ways of documenting this gate:

1) as an AND symbol with negated output,
2) as an OR symbol with negated inputs.

The two drawings are functionally equivalent and give the same result.

The NAND symbol is best described as an AND gate with ACTIVE LOW output.
The Negative-OR symbol is best described as an OR gate with ACTIVE LOW inputs.

ACTIVE HIGH or POSITIVE LOGIC means that the signal is presented with a high voltage or logic 1.
ACTIVE LOW or NEGATIVE LOGIC means that the signal is presented with a low voltage or logic 0.

Which symbol should you choose?

The proper answer is, choose the symbol that better reflects the boolean function to be implemented for ACTIVE HIGH logic.
Choose the AND symbol for AND function of the inputs.
Choose the OR symbol for the OR function of the inputs.

Here is an example:

You need a logic gate to reset your MCU which takes ACTIVE LOW input into the /RESET pin.
There are two ways that the MCU will be reset, either from a pushbutton OR from a POWER-ON RESET circuit.

Both of these inputs are ACTIVE LOW. Hence the proper symbol to choose is an OR gate with ACTIVE LOW inputs and outputs while in hardware the function is implemented with a 7408 AND gate.

Note that a bar is drawn over the symbol name to indicated that it is an ACTIVE LOW signal. The bar over the symbol and the bubble both represent the same thing. Do not think of cancelling one with the other even though this is logically correct.

This originally appeared in this thread 12 years ago.

Let the bubbles align wherever they happen to be.
The one option you have is with a NOT gate and the non-inverting buffer. Align the bubble next to another bubble. This helps when analyzing logic circuits visually. When you encounter two bubbles on the same connection, they cancel. We visualize this as being able to slide beads along a wire freely.

This is the origin of the statement presented by the original post (thread starter).

There are situations where having two bubbles on the same wire is not possible. You are allowed to slide a single bubble along the wire in order to visualize what hardware gate to choose when you want to minimize chip count. This is a way of doing the boolean algebra in a visual manner.

Conclusion

I would change the statement posted by the thread starter to read:

Draw the symbol that best represents the POSITIVE LOGIC function of the function required.
That is, are you representing the AND function of the inputs or are you representing the OR function of the inputs?

Wherever possible, choose the bubbles to reflect the nature of the signal, whether ACTIVE HIGH or ACTIVE LOW.

#### AnalogKid

Joined Aug 1, 2013
10,218
Hello, when we studied digital electronics we learned that:
Whenever possible, choose gate symbols that so that bubble outputs are connected to bubble inputs, and nonbubble outputs are connected to nonbubble inputs.
Is that due to technical reasons, or simply to good manners in design?
Both.

Manners: It conveys the intent of the original designer in a clear and unambiguous manner.

Tech: Particularly for inputs, it indicates whether the input is operating as positive-true or negative-true logic. For example, a bubble on a clock input indicates that the circuit is clocked on the negative-going edge of the input waveform. This is critical information.

ak

#### dl324

Joined Mar 30, 2015
15,510
when we studied digital electronics we learned that:
Whenever possible, choose gate symbols that so that bubble outputs are connected to bubble inputs, and nonbubble outputs are connected to nonbubble inputs.
I was never taught to do that and haven't seen it in any schematics.

For example this CD4029 counter:

It would make sense to DeMorganize an AND function to an OR function if the AND was being used as an OR gate.

#### boostbuck

Joined Oct 5, 2017
273
Is that due to technical reasons, or simply to good manners in design?
Neither - it is a simplification of design discipline to align either positive or negative logic design to the physical implementation chosen.

The use of 'mixed logic' (both positive and negative together) to separate logic from implementation is described in "The Art of Digital Design" (my university textbook way back, a great book).

#### AnalogKid

Joined Aug 1, 2013
10,218
I was never taught to do that
I was. At least, I remember it coming up in class and being in the textbook. I think it is buried in an old MIL spec, but it rarely is followed to the letter.

It is interesting to me that just about everyone is used to bubble inputs on multi-input gates (and both bubble and non-bubble inputs in the same gate in CPLD and FPGA schematic-entry software), but that many people cannot grasp the function of an inverter with a bubble input.

ak