What circuit topology are you assuming?

Ok, I see the problem with my answer. I was assuming CE topology.

 

Unisa (University of South Africa)

The rule of thumb I was taught was to assume a beta of 10 when operating a transistor in saturation mode. That conforms to the data given in the datasheets I referenced.

Using that guideline, the transistor wouldn't have been in saturation for the initial conditions.

Some use a beta of 20, but this is the first time I've seen anyone assume a beta of 150...

If, somewhere, you're being told to expect unreasonable circuit parameters (e.g. hypothetical situations), it might be okay. But as it stands; can't happen, won't work.

 

I think we can ignore what we know from practice and just use the numbers given in the question.

What is max Ic @ Vc = 10V?
What is max Ic @ Vc = 15V?

Given Ib = 500μA and beta = 150, what are we demanding of the circuit?

 

I don't "think" they are saying that the transistor beta is 150 in saturation. I've almost never seen a transistor problem even state a beta in saturation, but rather always an assumed Vce(sat), so any beta that is also given is generally meant to be the beta when not in saturation. The normal model for hand computations is that the nominal beta applies up until the Vce(sat) is reached and at that point it stays at that Vce as base current is increased. It's a model that, on the surface, seems pretty unrealistic, but for most designs it is more than good enough.

 

I think we can ignore what we know from practice and just use the numbers given in the question.

What is max Ic @ Vc = 10V?
What is max Ic @ Vc = 15V?

Given Ib = 500μA and beta = 150, what are we demanding of the circuit?

Then what criterion is used to determine if it is or is not in saturation? That ANY collector current less than Ib*beta means the device is in saturation? I guess this is actually consistent with the simplest piecewise linear active/saturation model, when you think about it.

 

Let us look at it from an experimental perspective.

Suppose Vsupply = 10V
R2 = 180Ω
R1 = 10kΩ
Vin = 5V

Would one expect the transistor to be turned on?
The supply can only supply max Ic = 10V/180Ω = 55mA
A beta of 150 is asking for 0.5mA x 150 = 75mA

The next question is, how does one determine VCE given this limited amount of data?

 

Hi,

First, no, they are not stating that Beta is 150 during saturation, they are just stating the active region Beta and do not specify the sat Beta. We can guess at this, and although it does seem high, that's not our problem.

In order to get something that resembles Vsat, we need a Beta of about 100. That is because with a base current of only 500ua we need a 9v drop across the 180 ohm resistor which leaves us with a paltry 1v for Vsat for the starting point in this problem. We could assume a little more if we dont like the 100 figure for Beta at saturation, but lets go with that for a moment.

Next, when we increase Vcc to 15 volts, with Beta=100 the Vce would rise to a very non paltry 6 volts, which is clearly out of sat, but now that we know it must be out of sat for that condition we apply the more correct condition of Beta=150 and we get Vce=1.5 volts.
1.5 volts is a little high to be called in saturation, so i would have to vote for "it's out of sat now" because the collector current is only 75ma, but i would have preferred to see a slightly higher Vce at this point. Someone could check the data sheet for these conditions and see if it is reasonable. I would have also preferred to see a more reasonable Beta for when the device is in sat.

I assume CE circuit because the resistor is in the collector circuit.

 

Beta is a distractor for this problem. It's doing a good job.

I took the problem as hold Ib at a constant 500 uA. As you increase Vcc to 15, when does the transistor come out of saturation.

Like most questions, one must discover the stem of the question to get rid of the fluff (distractors).

 

I took the problem as hold Ib at a constant 500 uA. As you increase Vcc to 15, when does the transistor come out of saturation.

Good question. How does one determine this?

 

Hi,

First, no, they are not stating that Beta is 150 during saturation, they are just stating the active region Beta and do not specify the sat Beta. We can guess at this, and although it does seem high, that's not our problem.

In order to get something that resembles Vsat, we need a Beta of about 100. That is because with a base current of only 500ua we need a 9v drop across the 180 ohm resistor which leaves us with a paltry 1v for Vsat for the starting point in this problem. We could assume a little more if we dont like the 100 figure for Beta at saturation, but lets go with that for a moment.

Next, when we increase Vcc to 15 volts, with Beta=100 the Vce would rise to a very non paltry 6 volts, which is clearly out of sat, but now that we know it must be out of sat for that condition we apply the more correct condition of Beta=150 and we get Vce=1.5 volts.
1.5 volts is a little high to be called in saturation, so i would have to vote for "it's out of sat now" because the collector current is only 75ma, but i would have preferred to see a slightly higher Vce at this point. Someone could check the data sheet for these conditions and see if it is reasonable. I would have also preferred to see a more reasonable Beta for when the device is in sat.

I assume CE circuit because the resistor is in the collector circuit.

How did you determine VCE?

 

Beta is a distractor for this problem. It's doing a good job.

I took the problem as hold Ib at a constant 500 uA. As you increase Vcc to 15, when does the transistor come out of saturation.

Like most questions, one must discover the stem of the question to get rid of the fluff (distractors).

I don't think that beta is the distractor -- you need it to answer the question. The whole business about being in saturation with Vcc at 10 V is the distractor. Imagine that the question had been the following:

A certain 2N3904 with hfe= 150, Ib = 500 uA, Vcc = 15V and Rc = 180 ohm.

1.Is the transistor in saturation?

2. What is Vce?

No one would be having any problems with it.

You first assume the transistor is not in saturation. You then determine the collector current. You then determine the collector voltage. You then determine Vce. You then ask if this is consistent with it not being in saturation.

Very different answer than if they had stated that beta was 300, so beta is NOT a distractor.

We also don't care about WHEN the transistor comes out of saturation, we only care about whether or not is IS out of saturation at Vcc = 15 V.

 

Good question. How does one determine this?

Since it's a continuous process, there is no answer. You either have to define an arbitrary criterion, such beta falling below a specific value or Vce reaching a specific value, but in either of those cases you need to know have beta changes with Ib and Vce. Or you use a model that has a definite transition point, such at the piecewise linear model. In that case finding that point is easy. You analyze the circuit to find the point at which Vce = Vce(sat) and Ic = βIb assuming Vce is fixed in saturation and β is fixed in the active region. If we assume Vce(sat) is 0.3 V, then the transition point happens at Vcc = 13.8 V.

 

This question intrigued me and I had to determine this experimentally by raising the supply voltage gradually from 10V to 15V.

As far as I can tell, you cannot do this theoretically unless you have additional empirical information on the behaviour of the device at saturation.

For example, you need to look at the I-V characteristics of the transistor:

In the example shown in the graph above, the device is in saturation if IB = 500μA.
As you raise the supply voltage, the load line shifts up and to the right but remains parallel to the original line. (The slope of the load-line is the negative of the collector resistor value).

If the supply voltage is increased so that the load line crosses the IB = 500μA base-emitter bias current then the transistor will be out of the saturation region.

Note that the graph shown is a hypothetical one, not for a real device.
For a real device where beta is not constant, the upper traces become compressed, i.e. beta starts to fall, in other words, the spacing between the 400 an 500μA lines is smaller than the spacing between the 300 and 400μA lines.

I can post later what the curves for a real 2N3904 should look like using a real transistor curve tracer.

 

Why we cannot assume fixed β = 150 in the active region and do the problem like this:

Ic_ max = 10V/180Ω ≈ 55.6mA and 15V/180Ω ≈ 83.4mA .

So for Ib = 500μA we have Ic = 75mA form this we can see that the BJT come out of a saturation for Vcc = 15V.



What is wrong with this approach ?

 

The question that we are now pondering is at what supply voltage the transistor comes out of saturation?
We know it is somewhere between 10V and 15V with this example question.
The problem is that for a real device, beta is not constant and making the assumption that beta = 150 is a false assumption.

 

We can. Notice the breakover point in the simulation. It's right about 13.8 V. Sound familiar?

 

The question that we are now pondering is at what supply voltage the transistor comes out of saturation?
We know it is somewhere between 10V and 15V with this example question.
The problem is that for a real device, beta is not constant and making the assumption that beta = 150 is a false assumption.

So is assuming the Vbe = 0.7 V, yet we do it all the time.

Virtually no model of how anything works can't be categorized as a bunch of false assumptions. The question isn't whether the assumptions are false or not -- we know they almost certainly are -- but whether they are good enough to yield answers that are close enough to be useful enough for the task at hand.

If you want to ponder at what point the supply voltage comes out of saturation and how that is affected by the falsity of the assumption that the beta is not constant in the linear region, then you are pondering things at a level of detail that requires you to very precisely define what the dividing line is between being in saturation and not being in saturation.

If you want to take the change in beta into account, then you have to have a model for how beta changes. And it will be based on false assumptions to one degree or another.

We often talk about data sheets using a beta of 10. But this is NOT when they declare that the device has suddenly transitioned from active to saturation modes. If you asked any person that makes transistors if that same transistor was in saturation when the beta was 11, they would say of course it is. That arbitrary value of beta is merely the conventional operating point at which the saturation voltage is measured for the purpose of putting it in the datasheet.

 

The problem is that for a real device, beta is not constant and making the assumption that beta = 150 is a false assumption.

I can repeat this experiment in real world and I will get similarly result (all I need to do is to tweak Rc value ).

 

@WBahn

I don't have a problem with making the assumption that VBE = 0.7V. This comes from the diode equation.

How did you arrive that VCE(sat) = 0.3V?

 

For a real device where beta is not constant, the upper traces become compressed, i.e. beta starts to fall, in other words, the spacing between the 400 an 500μA lines is smaller than the spacing between the 300 and 400μA lines.

I can post later what the curves for a real 2N3904 should look like using a real transistor curve tracer.

And those real curves will deviate from that hypothetical model in several ways.

We commonly use a range of device models, both for hand calculations and for computer simulation.

The simplest transistor model, and the one that most students are first introduced to and that actual designers probably use more often than not, at least for initial design sketching, is that the collector current is directly proportional to the base current as long as Vce > 0 and zero otherwise. In this model the Ic line at a given Ib is flat and goes right to the vertical axis. There IS no such thing as saturation, only active and cutoff. We use this model all the time.

The next step up is the one that puts an a fixed Vce(sat). Now our Ic lines stop short of the vertical axis and we have a sharp transition from active to saturation to cutoff. This model is extremely heavily used in practice because it is simple and lets us get answers near the saturation point that are usually good enough when the prior model might not be.

The next step us usually to slant the saturation line as your characteristic shows. This allows for a continuous beta, which is useful at times, and for better fidelity in the saturation region. We generally don't need this for hand calculations, but computer sims really like it as it helps them converge. The slant is generally modeled by a low value resistor in the saturation region.

The next step is beta compression as Ic increases, which is what you are focusing on. As you say, this results in the spacing of the curves (for evenly spaced values of Ib) getting smaller as Ib increases.

The usual next refinement is to recognize that, in the active region, the Ic curve slant upward and to the right. If these are projected back to where they cross the horizontal axis we observe that they all cross near the same point, which we call the negative of the Early voltage. We can use this to apply the notion of an output resistance that closely approximates these lines.

Next we typically deal with the nasty discontinuities (in derivatives) at the transition points, which cause problems for simulators. We need a smooth, curved transition. Here we usually acknowledge that treating the device as being current controlled has reached its useful limit and treat it as being voltage controlled. This leads to the Ebers-Moll model which is not only continuous, but continuously differentiable, which simulators love. It also marks the point where the models transition away from being practical for doing hand calculations. Beyond this point we rely heavily on simulations.

But even this model isn't good enough for many of the more demanding designs, particularly analog IC design. So over the years more complex physics-based models have been developed. These account for junction capacitances, carrier mobility, carrier lifetimes, and lots of other things. But while they are better, there are still to many cases for which they are not good enough, particularly for dealing with things like process variation and short-reach, long-reach, and orientation device mismatch issues (not to mention short-channel effects). So IC fabs use subcircuit wrappers around the transistor model to account for these things parametrically via curve fitting. The result can be models that contain hundreds of components and that, if printed out, take up several pages. But the result is also highly reliable and accurate models that can be used to simulate extremely demanding analog circuits with the expectation that they will function as expected on first silicon. But even these models have limitations. They are only good over a range of temperatures, for instance. So if we want the design to actually work at liquid nitrogen temperature, it is not sufficient to just set the similator temp to 77 K, we have to use a different model that has been characterized for that temperature region. The availability of such models is far from guaranteed, especially for logic processes. This factor alone can dictate which fab processes are considered as viable candidates.