Hello, In a slide below taken from the manual they say that maximal common model is Vdd-Vsg3+Vt1
two questions:
1.the last step from drain of M1 and gate of M1 the voltage drop is Vt1 ,its the condition which M1 will stay saturated.
However in the table they say that Vd-Vg>=-Vth
Why there is a minus in the Vth but in table they use +Vth as the condition for M1 will stay saturated.

2.What is the meaning of absolute value in the PMOS saturation condition?
Thanks.
https://aicdesign.org/wp-content/uploads/2018/08/lecture19-150211.pdf

 

2.What is the meaning of absolute value in the PMOS saturation condition?
Thanks.

I can make a stab at this one. They used absolute value so that the relation would stay the same for PMOS even though all voltages are negated from the NMOS ones.

I don’t like it much because it implies that you could invert any of the voltages and it would still be in the saturation region, which is not true. For example, make Vgs positive for the PMOS case and the inequality is unchanged after the absolute value, but the PMOS transistor is in cutoff with a positive Vgs.

 

1.the last step from drain of M1 and gate of M1 the voltage drop is Vt1 ,its the condition which M1 will stay saturated.
However in the table they say that Vd-Vg>=-Vth

Do the math
We have:
Vci_max = Vdd - Vsd3 - Vds1(sat) + Vgs1

We know that Vds should be larger or equal to (Vgs - Vth) to stay in saturation.
Therefor:
Vds1(sat) = Vgs1 - Vth1

From this, we have:
Vci_max = Vdd - Vsd3 - (Vgs1 - Vth1) + Vgs1 = Vdd - Vsd3 - Vgs1 + Vth1 + Vgs1 = Vdd - Vsd3 + Vth1

2.What is the meaning of absolute value in the PMOS saturation condition?

We use absolute value for simplicity, we simply want to have the same equation for NMOS and PMOS.
And for the PMOS, Vgs and Vth are negative.

 

We have an expression that takes care of saturation in M5.
V_Ic_min=Vss+Vds_5_sat+Vgs1
what is the logic in minimal common mode expression?
Why making sure M5 is saturation ensures lower value of V_in common mode?
Thanks.

 

Why making sure M5 is saturation ensures lower value of V_in common mode?

Because only as long as M5 stays in a saturation region, as long as the Iss current stays unchanged.

 

Why M5 condition is not maximal common mode input voltage condition ?

 

Why M5 condition is not maximal common mode input voltage condition ?

Are you asking about why M5 is not included in Vci_max ?
Why do you think that we must include M5 in Vci_max?