I tried to use the following circuit as training

That circuit will only provide an output pulse when power is applied, as there is no DC path for the base current to keep the transistor on after that.

You need to understand how transistors work, before you do a design with them.

 

I wrote a specific state machine what else is needed ?

Hello,I have upgraded the circuit you presented by putting a capacitor at the base thus creating a delay between M12 and Vout.
So my Vout comes after some time after M12 depending on the capacitor .( try8_united2.asc LTSPICE file is attached)
I want to upgrade further this circuit by creating another output which is the delay of Vout.
So by logic I want to use Vout as a switch signal and P12 as the signal the delayed line needs to pass threw.
So P12 will be delayed even further on another output.
In the photo named 2 i have triied to implement it.
The Qc_1 pulse opens and closes the NPN with R11 limiting resistor.

I connected again the 4.7u 47u but its not delaying the final signal as before in the first stage.
The full LTSPICE file called "double delay" is attached.
Where did i go wrong?
Thanks.