I don't know what you are referring to by "the RC branch" since you have two Rs.

R4 and C are connected in series. Does this not make them a branch?

With the current circuit, when switch is open Q2 will turn on taking the top of R5 to Vcc. But the other end of R5 will be open and no current will flow through it.

I knew something was wrong. I think we are using different tools, and mine is broken . I assume you're using LTspice (which I use for transient analysis but it gets difficult with switches involved). I'm using a simulator (http://www.falstad.com/circuit/).

On my end, for some reason, the switch is open and Q1 has current through it which should not be happening if it is OFF.

 

R4 and C are connected in series. Does this not make them a branch?

Okay -- now I know what you are referring to. Yes, R4 and C are a "branch" -- Although R5 is not technically in a branch with R4 and C, when Q1 is ON they are effectively in series and so, somewhat sloppily, the "branch" terminology will get used to apply to circuits that are conditionally in series.

I knew something was wrong. I think we are using different tools, and mine is broken . I assume you're using LTspice (which I use for transient analysis but it gets difficult with switches involved). I'm using a simulator (http://www.falstad.com/circuit/).

On my end, for some reason, the switch is open and Q1 has current through it which should not be happening if it is OFF.

I'm not using any simulator at all for this so far. What values are you using for R1, R2, and R3? If R1 is too large (relative to R2 and R3) you will get current flowing in the base of Q2 that then flows down through R3 and then through R2 and on into the base of Q1 thus turning them both on. To avoid this, you need to keep the voltage at the junction of R1 and R2 well below the 0.6V nominal turn-n voltage for Q1.

I don't think you've hinted yet at the kind of time constants are capacitance values you are talking about, so I'm just going to make some up. Let's say that your capacitor is 10uF and you want time constants that are in the 1ms range. That means that you want the series resistors to be in the 100Ω range and that your peak current draws will be in the Vcc/100Ω range. Let's make Vcc=10V, so that's 100mA. In order to put the transistors hard into saturation, you normally want at least 1/10 of the collector current for the base current, so that's 10mA. With the switch off you ideally want nearly all of the voltage to be dropped across R3. We'll allow 0.7V for the Vbe of Q2 and no more than 0.2V for Vbe of Q1. so that will be about 9.1V at 10mA which will require a resistor of about 910Ω (1kΩ is probably acceptable). We also want all of that 10mA to flow through R1 with 0.2V across it, which means a resistor value of no more than about 20Ω, which is pretty small. When the switch is closed you will have 500mA in that resistor which is 5W of power. We can probably use 47Ω but not much more and that still gives us nearly 250 mA and over 2W.

So while your topology is okay on paper, sizing the values is difficult because you have to meet conflicting requirements. How about a slightly different topology in which the base current for both transistors always goes through a single resistor that is connected between them. Then two other resistors are used to shunt current around the transistor that is supposed to be OFF?

 

...If R1 is too large (relative to R2 and R3) you will get current flowing in the base of Q2 that then flows down through R3 and then through R2 and on into the base of Q1 thus turning them both on. To avoid this, you need to keep the voltage at the junction of R1 and R2 well below the 0.6V nominal turn-n voltage for Q1.

Ah! This is it! I had tried this form before, but the value for R1 was causing Q1 to turn on too...
I fully appreciate that you guys don't just solve problems for people needing help; I will now remember this one for a really long time!

I don't think you've hinted yet at the kind of time constants are capacitance values you are talking about, so I'm just going to make some up. Let's say that your capacitor is 10uF and you want time constants that are in the 1ms range. That means that you want the series resistors to be in the 100Ω range and that your peak current draws will be in the Vcc/100Ω range. Let's make Vcc=10V, so that's 100mA. In order to put the transistors hard into saturation, you normally want at least 1/10 of the collector current for the base current, so that's 10mA. With the switch off you ideally want nearly all of the voltage to be dropped across R3. We'll allow 0.7V for the Vbe of Q2 and no more than 0.2V for Vbe of Q1. so that will be about 9.1V at 10mA which will require a resistor of about 910Ω (1kΩ is probably acceptable). We also want all of that 10mA to flow through R1 with 0.2V across it, which means a resistor value of no more than about 20Ω, which is pretty small. When the switch is closed you will have 500mA in that resistor which is 5W of power. We can probably use 47Ω but not much more and that still gives us nearly 250 mA and over 2W.

So while your topology is okay on paper, sizing the values is difficult because you have to meet conflicting requirements. How about a slightly different topology in which the base current for both transistors always goes through a single resistor that is connected between them. Then two other resistors are used to shunt current around the transistor that is supposed to be OFF?

Understandable. Different topology but the same function with realizable values for R1-R3.

BTW I do appreciate your guys' time and help as I have no one else to ask; I'm not taking formal courses in EE because I'm largely self-taught.

 

Ah! This is it! I had tried this form before, but the value for R1 was causing Q1 to turn on too...
I fully appreciate that you guys don't just solve problems for people needing help; I will now remember this one for a really long time!

Thank you for recognizing that, for most people, in order to really learn something you have to struggle with it and make it yours.

View attachment 80868

While this is the topology (with regard to R4 and R5) that I was steering you toward, and while this is correct (with regard to R4 and R5), notice how the layout of the circuit doesn't make it apparent that there is a symmetry between the charge and discharge paths. A slight tweaking makes this much more apparent.