is the biasing proper?

will this circuit amplify 100 times? what is the maximum ac voltage i can give at the input?

please advise.

thank you in advance,
amrith.s

 

verification, Vcc is 100v?

 

i notice that you dont have any coupling capacitors in the schematic, is that on purpose or just an oops?

 

sorry Vcc=10v.

verification, Vcc is 100v?

 

no,i just omitted it because anyway its not going to affect the calculations that we may do manually. may be it will affect at real time.
ok, then lets take Cin=1u F.

thank you,

i notice that you dont have any coupling capacitors in the schematic, is that on purpose or just an oops?

 

ok, ill assume that there is coupling capacitors for Cin, Cout, and across the emitter resistor. and with a Vcc of 10 volts.

Vb = (Vcc*R2)/(R2+R3) = (10V*7.5Ko)/(7.5ko+92.5ko) = 0.75V

Ve = Vb-Vbe = .75v - .7v = 50mV

so Ie and Ic will be about 893uA, as you can see a higher Vb is needed, try 12k for R2

 

If the goal that amtirhs04 is trying to achieve is the linear amplification of the input signal, it seems that increasing R2 from 7.5K to 12K will cause the transistor to enter into saturation without any signal being applied at the input.

The 7.5K appears to result in placing the quiescent DC voltage at the collector at 5.0V which is about 50% of the 10V power supply. While not ideal, 5.0V gives the signal at the collector enough headroom to swing + or - 4 volts without saturating the transistor. That would mean that the maximum input would be around + or - 40 millivolts.

hgmjr

 

yes, you are right hgmjr, i was hoping someone would catch that.

 

ya hgmjr,
but how did you get that value +/-4V at collector? can you please teach me?

thank you,
amrith.s

If the goal that amtirhs04 is trying to achieve is the linear amplification of the input signal, it seems that increasing R2 from 7.5K to 12K will cause the transistor to enter into saturation without any signal being applied at the input.

The 7.5K appears to result in placing the quiescent DC voltage at the collector at 5.0V which is about 50% of the 10V power supply. While not ideal, 5.0V gives the signal at the collector enough headroom to swing + or - 4 volts without saturating the transistor. That would mean that the maximum input would be around + or - 40 millivolts.

hgmjr

 

The figure of + or - 4 volts at the collector is based on the fact that in a transistor amplifier it is a good idea not to drive the collector too close to the emitter or distortion of the output will result. I somewhat arbitrarily chose not to allow the input signal to drive the collector any closer to ground than +1 volt. That meant that the output could swing from +5V (its quiescent setpoint) negative to +1V. This is a difference of 4 volts. If symmetry of the output signal is to be preserved then that would imply that the positive most signal would be +9V.

The difference between +9V and +1V is 8V so I took the output to swing + or - half of that voltage which came to 4V. This signal would be centered on +5V.

hgmjr