4-bit synchronous counter which is counting upwards from 3 to 12?

Papabravo

Joined Feb 24, 2006
17,297
I'll give you two hints which may help you, at the risk of getting banned
First: The counter must operate in two modes which are:
  1. Count, that is "increment the count by 1" on the next clock edge
  2. Load, that is "do a parallel load" operation of the data on the D input. The thing you are primarily interested in "loading" is the value 3 or 0b0011 which is a constant.
Second: When the counter reaches 12 (0b1100) you need to switch from Count to Load before the next clock edge and once the Load has taken place you must switch back to Count before the subsequent clock edge

That says nothing about how you accomplish the ultimate goal but is does give you a 10,000 foot overview.
If you want extra credit on this assignment, do somethin sensible if the counter gets into an illegal state. What is an illegal state? Glad you asked. Any of the following states are illegal:
0, 1, 2, 13, 14,15 and there are ten legal states which are all the rest.
 

Papabravo

Joined Feb 24, 2006
17,297
Yes that is a pretty good start, but I see a mistake on line 12. The next state after 12 should be 3 or 0b0011
You could also replace the X's in the next state columns with 3' or 0b0011 and that would map all illegal states to the desired starting state on the next clock pulse.
Since you are using JK flip-flops, there are particular values of J & K that will load a constant value into the output. That is what you want to use to load the starting value of 3 or 0b0011.
Also it does not seem reasonable that there are x's in any of the JK columns. They each need to be set to do one of the following:
  1. Clear to "0"
  2. Set to "1"
  3. Toggle
  4. Hold
 

Thread Starter

Sedus

Joined Mar 25, 2021
31
According to my notes
  1. Clear to "0" is 01
  2. Set to "1" is 10
  3. Toggle is 11
  4. Hold is 00
So if I have 0 and I want 0 I can hold and I can clear to 0 too, this is why 0X, or is it nonsense?
 

dl324

Joined Mar 30, 2015
13,534
I assume I need this table to build gates. Is this correct?
It would be helpful if you posted the complete text for the problem. In your original post, you were using T flip flops; now you're using JK.

Is that the way you were taught to build a truth table? I was taught to use gray code to facilitate transferring the data to Kmaps. That requires you to be able to read binary numbers, but that isn't difficult.

Kudos to you for minimizing cell width and centering data. It makes it much easier to read.

I'm glad to see that you're using A as the LSB. Too many are teaching students to use A as the MSB as you showed in your first schematic.
 

Papabravo

Joined Feb 24, 2006
17,297
According to my notes
  1. Clear to "0" is 01
  2. Set to "1" is 10
  3. Toggle is 11
  4. Hold is 00
So if I have 0 and I want 0 I can hold and I can clear to 0 too, this is why 0X, or is it nonsense?
I see what you are saying and I've always been more comfortable with knowing that on each clock edge there was only one possible thing that was going to happen. Implemented in discrete parts there may be some advantage to the use of don't cares, but they make me nervous. I don't know why. It's probably a personality defect. When it comes to problem solving there are three steps:
  1. First, make it work
  2. Second, make it smaller, faster, whatever
  3. Last, make it elegant.
I don't know if this approach is universal but it has always worked well for me. Your mileage may vary. I'm here to help, not throw stones.
 

Thread Starter

Sedus

Joined Mar 25, 2021
31
I see what you are saying and I've always been more comfortable with knowing that on each clock edge there was only one possible thing that was going to happen. Implemented in discrete parts there may be some advantage to the use of don't cares, but they make me nervous. I don't know why. It's probably a personality defect. When it comes to problem solving there are three steps:
  1. First, make it work
  2. Second, make it smaller, faster, whatever
  3. Last, make it elegant.
I don't know if this approach is universal but it has always worked well for me. Your mileage may vary. I'm here to help, not throw stones.
Summed up, 0X is good but you more comfortable with the other method?
 

Papabravo

Joined Feb 24, 2006
17,297
Summed up, 0X is good but you more comfortable with the other method?
Yes, until I get it working. Then all possible optimizations are on the table. The more straightforward and unambiguous a design is the easier it is to debug if (when) things go wrong. After you get it working it is easy to make small changes and look for potential side effects. If the implementation is in an FPGA with logic gate resources to burn then I wouldn't even bother with optimization. It would be a waste of time if 90% of the gates in the FPGA are unused.
 
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