Synchronous counter designs don't use preset or clear.so U7 got all 3 input to high when counter switching 7 to 8.
Go back and check your notes. You either start with a state diagram or a truth table.
Synchronous counter designs don't use preset or clear.so U7 got all 3 input to high when counter switching 7 to 8.
It would be helpful if you posted the complete text for the problem. In your original post, you were using T flip flops; now you're using JK.I assume I need this table to build gates. Is this correct?
I see what you are saying and I've always been more comfortable with knowing that on each clock edge there was only one possible thing that was going to happen. Implemented in discrete parts there may be some advantage to the use of don't cares, but they make me nervous. I don't know why. It's probably a personality defect. When it comes to problem solving there are three steps:According to my notes
So if I have 0 and I want 0 I can hold and I can clear to 0 too, this is why 0X, or is it nonsense?
- Clear to "0" is 01
- Set to "1" is 10
- Toggle is 11
- Hold is 00
Summed up, 0X is good but you more comfortable with the other method?I see what you are saying and I've always been more comfortable with knowing that on each clock edge there was only one possible thing that was going to happen. Implemented in discrete parts there may be some advantage to the use of don't cares, but they make me nervous. I don't know why. It's probably a personality defect. When it comes to problem solving there are three steps:
I don't know if this approach is universal but it has always worked well for me. Your mileage may vary. I'm here to help, not throw stones.
- First, make it work
- Second, make it smaller, faster, whatever
- Last, make it elegant.
Yes, until I get it working. Then all possible optimizations are on the table. The more straightforward and unambiguous a design is the easier it is to debug if (when) things go wrong. After you get it working it is easy to make small changes and look for potential side effects. If the implementation is in an FPGA with logic gate resources to burn then I wouldn't even bother with optimization. It would be a waste of time if 90% of the gates in the FPGA are unused.Summed up, 0X is good but you more comfortable with the other method?
Your table is correct except for when the count is 12.So if I have 0 and I want 0 I can hold and I can clear to 0 too, this is why 0X, or is it nonsense?
Did your instructions give any requirements for the number of clocks required to count out of an illegal state?Im not sure 0,1,2 would be 3 or XXXX?
Then treating the invalid counts as don't cares could simplify the logic.
Yes.XXXX is a dont cares?
You don't need to for 13-15, but the reason for 12 should be obvious.why I must use 3 at 12,13,14,15?