# A 4-bit synchronous up counter that stops at 9

#### Copo9007

Joined Jan 1, 2024
2
Hey guys, I have managed to make circuit that counts up from 0 in logicly but I'm kinda stuck on how to make it stop at 9, help would be much appreciated.

screenshot of the circuit is attached.

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#### WBahn

Joined Mar 31, 2012
30,088
Is this a school assignment of some kind?

#### Copo9007

Joined Jan 1, 2024
2

#### Papabravo

Joined Feb 24, 2006
21,228
I see you are using JK Flip-Flops. Your drawing is very hard to follow. It would be an aid to understanding if you learned how to draw a more conventional schematic.

Hints:
1. Look for a combination of inputs that will inhibit counting.
2. Then look for a combination of inputs that will clear the counter, by setting each bit to 0.
3. Changes should only happen on the clock edge, so using the set and clear inputs, which are normally asynchronous, is a sub-optimal way to do this.
One you have identified the available and useful control inputs, the clouds will part, and you will see your way to the promised land. Well....maybe not, but at least you will be closer to the solution of your problem.

#### WBahn

Joined Mar 31, 2012
30,088
MOD NOTE: Moved to Homework Help.

It's very hard to follow wiring diagrams like that, so (as Papabravo noted) it will really help everyone (including you) to learn how conventional logic diagrams are drawn.

Do you know what a state diagram or a transition table is?

I strongly recommend designing circuits using fully-synchronous logic unless you have a damn-good reason to do something asynchronous. While damn-good reasons do exist, there are demons that cruise those waters.

#### crutschow

Joined Mar 14, 2008
34,472
You have drawn a wiring diagram which is used to fabricate the circuit, not to show how it works.
The language of electronics is a schematic.

#### dl324

Joined Mar 30, 2015
16,944
Welcome to AAC!
I have managed to make circuit that counts up from 0 in logicly but I'm kinda stuck on how to make it stop at 9
It would be helpful if you posted the complete text for the problem.

This is how the pros draw counters.
Texas Instruments 74160 from 1976 databook:

Motorola 2000 databook:

I don't care for this style, but it's easier to read than yours.

Sadly, I've seen instructors on YouTube draw schematics that weren't much easier to read than yours. And they label the flip flops backwards (MSB is A, when LSB should always be A).

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#### Papabravo

Joined Feb 24, 2006
21,228
There are four possible combinations of J & K for each Flip-Flop. Write down for us to see what each possible combination does.
Hint: one of the combinations causes the JK flip-Flop to toggle. That means, that on the next clock edge the state will change from a 1 to a 0 or a 0 to a 1. So what do the other three combinations do?

#### dl324

Joined Mar 30, 2015
16,944
Even from the messy schematic, you can see that the OP is using all of the flip flops as toggle. Which is a waste of the benefit of using a JK flip flop...

#### Papabravo

Joined Feb 24, 2006
21,228
Even from the messy schematic, you can see that the OP is using all of the flip flops as toggle. Which is a waste of the benefit of using a JK flip flop...
I'm pretty sure he is unaware of doing anything except toggling. At least based on the questions he is asking, it seems like setting J & K to "hold the present state" is completely beyond his comprehension. Let alone the other two functions that are available.

#### eetech00

Joined Jun 8, 2013
3,961
This is how the pros draw counters.
Texas Instruments 74160 from 1976 databook:
Motorola 2000 databook:
Yes. But those schematics are drawn in the context of integrated circuits.
I wouldn't recommend that style as a general schematic drawing example.

#### WBahn

Joined Mar 31, 2012
30,088
I'm pretty sure he is unaware of doing anything except toggling. At least based on the questions he is asking, it seems like setting J & K to "hold the present state" is completely beyond his comprehension. Let alone the other two functions that are available.
He IS using "hold the present state" -- that's what a T Flip Flop does when T is no asserted, which is happening for him most of the time -- the only time T is asserted (i.e., J=K=1) is when the Q output of all prior FF is 1.