Good evening, I designed a synchronous counter with the arbitrary sequence of: 1000, 1010, 0010, 0110, 0100, 0101, 0001, 1001,...
After doing all the necessary steps (state diagram, new state table, flip-flop transition table, Karnaugh maps, logic expressions of flip-flops, and finally counter implementation), I simulated the obtained circuit with Isis Proteus and the results were convincing.
But, is there a more elegant way to do that? because to avoid the case 0000 I used the set input of FFA to begin the count with 1000.
Thanks.

 

The only improvement would be to construct an illegal state detector for 8 of the 16 states that are not in the sequence and make the next state be ANY legal state. The result of this is there can be a single period with an illegal state, but the machine will quickly fix itself. The other thing you can do is have an asynchronous reset that will not allow an illegal state at startup or when an illegal state is detected.

 

Just use the Q' output of the first counter as that FF's output. When when the counters are all reset, they reset to state 1000.

Other than that, you are relying on the FFs starting up in a reset state. Your simulator might work that way, but the real world doesn't. So you want a reset input and should make it act as a power-on-reset.

You also want to decide how to handle the eight states that are not in your sequence. If the problem statement doesn't say how to handle them, you get to decide. The one thing that you are virtually guaranteed of is that, sooner or later, your systme WILL end up in one of those states. Some options are:

1) Do nothing and let them just do whatever they do.

This is NOT a good choice, as nearly anything can happen.

2) Have the system enter a trap state.

This is a state that, once entered, can only be exited by doing a reset.

3) Have the system perform a reset.

Either immediately via the asynchronous reset, or upon the next clock.

4) Have the system get back into a legal state.

Either on the next clock, or at least eventually.


Each of these approaches is the proper approach for different circumstances. You need to consider what the system is being used for and which action is the best (or least worst) for that system.

 

Your schematic is virtually unreadable. Post your truth tables and Kmaps so we can see what you designed.

Labeling the MSB A is backwards. Is that what they're teaching you?

You can learn a lot by looking at schematics drawn by professionals.

TI 74LS160:

 

The only improvement would be to construct an illegal state detector for 8 of the 16 states that are not in the sequence and make the next state be ANY legal state. The result of this is there can be a single period with an illegal state, but the machine will quickly fix itself. The other thing you can do is have an asynchronous reset that will not allow an illegal state at startup or when an illegal state is detected.

Thanks for replay

 

Your schematic is virtually unreadable. Post your truth tables and Kmaps so we can see what you designed.

Labeling the MSB A is backwards. Is that what they're teaching you?

You can learn a lot by looking at schematics drawn by professionals.

TI 74LS160:
View attachment 283319

Flip Flop A is the MSB and FLIP FLIP D is the LSB.
Thanks again

 

But, is there a more elegant way to do that? because to avoid the case 0000 I used the set input of FFA to begin the count with 1000.

Does the problem specify how you should count out of invalid states?

Flip Flop A is the MSB and FLIP FLIP D is the LSB.

I can't believe how much of a chore it was to do things backwards after decades of doing it correctly...

 

How about a Seeeduino XIAO? Inexpensive, easy to re-program.

 

How about a Seeeduino XIAO? Inexpensive, easy to re-program.

Keep in mind that this is a homework problem in logic design.