What are the layout constraints that need to be followed while laying out a PLL?
S Thread Starter SDSI Joined Sep 16, 2016 10 Sep 17, 2016 #1 What are the layout constraints that need to be followed while laying out a PLL?
Alec_t Joined Sep 17, 2013 14,335 Sep 17, 2016 #2 They would obviously depend on whether the layout is at the silicon level, board level, or whatever. You need to provide more info.
They would obviously depend on whether the layout is at the silicon level, board level, or whatever. You need to provide more info.
