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VHDL signal assigment problem ?

A

Thread Starter

ajapyy

Joined Apr 27, 2013
6
this is my question :

We can use a signal assignment statement with inertial delay to remove
pulses that are smaller than a certain width. Using only signal
assignment statements, write a code fragment for removing positive
pulses that are greater than a certain width.

Thanks eveybody :)
 
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