# VHDL multiple asynchronous signal handling

#### mos_6502

Joined Dec 11, 2017
28
Hi everyone,
to realize an asynchronous project, I would need to manage different signals and understand when they change state, both from 0 to 1 and from 1 to 0.

The change from these signals should change an output signal, which drives another section of the circuit.

For this, I use:
Code:
process(signal_1)
begin
if something then
signal_out <='0';
endif;
end;

process(signal_2)
begin
if something then
signal_out <='1';
endif;
end;

In this case, I obtain an error:
Error (10028): Can't resolve multiple constant drivers for net "signal_out" .
For this reasons I try to insert all signals in one process, in this manner:

Code:
process(signal_1, signal_2)
begin
if rising_edge(signal_1)or falling_edge(signal_1)then
if something then
signal_out <='0';
endif;
endif;
if rising_edge(signal_2)or falling_edge(signal_2)then
if something then
signal_out <='1';
endif;
endif;
end;
But, in this case, I have the error:
Error (10628): […] can't implement register for two clock edges combined with a binary operator.

What is the correct way to get what I want?

#### kubeek

Joined Sep 20, 2005
5,726
I vaguely remember you either need one process for each edge, or separate if clause for rising and for falling.