A question about signal in VHDL

Thread Starter


Joined Dec 4, 2018
I know that signal in VHDL is "a wire", but i dont understand how it is implemented in the fpga... Where the data of the signal which i create is stored?

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Joined Feb 24, 2006
when i do :
signal a : integer range 0 to 20;

how the fpga implement it?
Assuming that your construct is valid syntactically, there are a variety of ways it could be implemented semantically and the specific method is up to the VHDL compiler and the FPGA maker. One way would be to implement a group of 5 Flip-flops which can hold any value in the range 0-31 as an unsigned integer. This group of flip-flops can also hold an integer in the range 0 to 20. Depending on other requirements there might be logic to detect invalid contents and reset the flip-flops to always contain a valid value.