Hi,
I know that signal in VHDL is "a wire", but i dont understand how it is implemented in the fpga... Where the data of the signal which i create is stored?

someone?

 

someone?

Your question is incoherent. Data in a signal you create is not stored....anywhere.

 

Your question is incoherent. Data in a signal you create is not stored....anywhere.

when i do :
signal a : integer range 0 to 20;

how the fpga implement it?

 

when i do :
signal a : integer range 0 to 20;

how the fpga implement it?

Assuming that your construct is valid syntactically, there are a variety of ways it could be implemented semantically and the specific method is up to the VHDL compiler and the FPGA maker. One way would be to implement a group of 5 Flip-flops which can hold any value in the range 0-31 as an unsigned integer. This group of flip-flops can also hold an integer in the range 0 to 20. Depending on other requirements there might be logic to detect invalid contents and reset the flip-flops to always contain a valid value.

 

Hello,

There are several makers of VHDL software.
It can be that the functions can differ between them.
The eye has some VHDL books for download:
https://the-eye.eu/search/?s=VHDL

Also the internet archive has some documents about VHDL:
https://archive.org/search.php?quer...type:"texts"&and[]=loans__status__status:"-1"

bertus