VHDL
begin
x<=not ( (not a and not b) or (not a and not c) or (not a and not d)
or ( not b and not c) or (not b and not d) or ( not d and not c) ).
create truth table that describes logic circuit?
I used a'b' + b'c' + a'd' +b'c' + b'd' + d'c' then negated again. used
demorgans and simplified to abcd. abcd would be 1 in truth table.
answer in book indicates abcd ab'cd a'bcd abc'd. Having trouble understanding their tt.
any help would be welcomed. Thanks
begin
x<=not ( (not a and not b) or (not a and not c) or (not a and not d)
or ( not b and not c) or (not b and not d) or ( not d and not c) ).
create truth table that describes logic circuit?
I used a'b' + b'c' + a'd' +b'c' + b'd' + d'c' then negated again. used
demorgans and simplified to abcd. abcd would be 1 in truth table.
answer in book indicates abcd ab'cd a'bcd abc'd. Having trouble understanding their tt.
any help would be welcomed. Thanks