I was writing my code for non restoring division algorithm in VHDL and experiencing some problem, in the code I have written 16 bit division, but while doing synthesis waveform I didn't get the correct result code is shown below:
Rich (BB code):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity division is
Port ( q : in STD_LOGIC_VECTOR (15 downto 0);
m : in STD_LOGIC_VECTOR (15 downto 0);
qf : out STD_LOGIC_VECTOR (15 downto 0);
rf : out STD_LOGIC_VECTOR (15 downto 0);
clk:in std_logic;
rst:in std_logic);
end division;
architecture Behavioral of division is
signal aq,m_sub,m_add:STD_LOGIC_VECTOR (32 downto 0);
signal m_neg: STD_LOGIC_VECTOR (16 downto 0);
signal count:std_logic_vector(4 downto 0);
begin
m_neg<=(not('0'&m))+1;
process(clk,rst,m)
begin
if(rst='1') then
count<="00000";
aq<="00000000000000000"&q;
m_add<='0'&m&"0000000000000000";
m_sum<=m_neg&"0000000000000000";
elsif rising_edge(clk) then
count<= count+"00001";
if(count<="1111") then
aq<=aq(31 downto 0)&'0';
if(aq(32)='1') then
aq<=aq+m_add;
else
aq<=aq+m_sub;
end if;
aq(0)<= not(aq(32));
elsif(count="10000") then
if(aq(32)='1') then
aq<=aq+m_sum;
else
aq<=aq+m_sub;
end if;
else
aq<=aq;
end if;
end if;
qf<=aq(15 downto 0);
rf<=aq(31 downto 16);
end process;
end Behavioral;
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