Time and hold time violation in VHDL problem.


Joined Dec 13, 2021
Assuming this is not homework / a general question, but a specific problem your seeing,

Timing is first of done between registers,
registers on the same clock is easiest,
setup is that data does not manage to get out of one register in time to get into the next

Either your device is to slow, you clock is to fast , or you have to much combinational logic between registers.

You need to look at the timing report for your device,
and see what paths are the problem