Hi,

The CD40192 specifies minimum pulse widths for the various inputs. It also lists some propagation delays from this input to that output but only maximum and typical values, no minima.

Given the attached circuit, when the CD4028 counts down from S0 to S9, with a very short propagation delay is there the possibility of some kind of race condition? S9 will trigger load on the CD40192 which will program S9 low thereby short-cutting the pulse width on the load input to below minimum specification?
Or, S9 goes low and thus the load has obviously already occurred then there can never be a race condition? The same reasoning may be applied to S4 -> MR.

 

...only maximum and typical values, no minima.

Always design (and analyze) around "max" and "min" stated values. These are guaranteed by the manufacturer under specified operating conditions.

If no min (or max) is specified -- and you think you need a value for your design -- you are treading in dangerous waters.

 

Always design (and analyze) around "max" and "min" stated values. These are guaranteed by the manufacturer under specified operating conditions.

If no min (or max) is specified -- and you think you need a value for your design -- you are treading in dangerous waters.

I understand. But if you follow my reasoning of what might cause a race condition it's the unspecified minimum propagation delay(s) that could cause the minimum required pulse duration on the load input to not be met.

 

I understand. But if you follow my reasoning of what might cause a race condition it's the unspecified minimum propagation delay(s) that could cause the minimum required pulse duration on the load input to not be met.

I haven't analyzed your circuit. I am sure someone else will come around to do that shortly.

But, if you think there's a problem based upon an unpublished specification, you're probably right. Trust your gut.

 

Hi,

The CD40192 specifies minimum pulse widths for the various inputs. It also lists some propagation delays from this input to that output but only maximum and typical values, no minima.

Given the attached circuit, when the CD4028 counts down from S0 to S9, with a very short propagation delay is there the possibility of some kind of race condition? S9 will trigger load on the CD40192 which will program S9 low thereby short-cutting the pulse width on the load input to below minimum specification?
Or, S9 goes low and thus the load has obviously already occurred then there can never be a race condition? The same reasoning may be applied to S4 -> MR.

You actually have more problems than you realize.

Whenever you decide to use asynchronous logic in a sequential circuit, you take on the responsibility for doing the detailed design analysis that is required to ensure that it will work reliably. You are making an attempt to do so, which is much more than most people do. But you are overlooking a big potential problem. While you are correct to focus on the MR signal going to the counter IC, you are only considering the potential race condition. But you are assuming that the CD4028 has no static timing hazards, and this is not a good assumption. Your counter is providing four inputs to the CD4028, but those inputs are NOT going to change at exactly the same time, there will be some unpredictable skew between them, meaning that they will change in one of the several possible orderings with unpredictable delays between successive bits changing. The result will be a rapid succession of quasi-random output states between the initial state and the correct new state. The CD4028 will see each of these intermediate states and attempt to decode them. It may have time to decode some of them and not have time to decode others. The result is that there can be glitches on one or more of the CD4028's outputs, including the one you are using as an input to an asynchronous reset on the counter. As a consequence, you might see unexpected resets happing on seemingly random counts and that behavior will probably not be very repeatable -- change the temperature and the behavior will change.

As for your question regarding the impact of a fast load happening, what you are describing is theoretically possible, but is somewhat unlikely because there is a handshaking effect involved. You need to assert the load signal long enough for the registers to take on the preset values. But the 4028 will only stop asserting the load signal once the reset values have been successfully loaded, so, at first blush, it would appear that even if the minimum pulse width is violated that the actual pulse width is going to be long enough for the desired action to occur. But there is a caveat here -- you are loading four registers and it only takes one of them to change state for the 4028 to stop asserting the load. So what if one of them changes and the relaxation of the load happens so soon after that that one or more of the others don't successfully change because of the minimum pulse width violation? The chance of this happening are very small, but it could happen.

Similar reasoning applies to the MR signal generated by S4.

The bottom line is that this design is very risky and, as has already been pointed out, the fact that you need to know information not in the data sheet is a big red warning flag that you are designing a risky circuit.

 

There is no race problem. Analyse what happens on every clock pulse.

Firstly, you have a problem. The CD40192 counts UP on the rising edge while the DOWN input is HI.
Similarly, the UP input must be HI in order to count DOWN on the rising edge of DOWN. You need to fix that first.

While counting UP on the rising edge of UP, the counter will advance 0-1-2-3-. On the 4th clock pulse, DCBA of CD4028 becomes 0100 and S4 goes HI. This resets CD40192 and S4 goes back to LO. Thus S4 only stays HI for a short time. This is determined by the total propagation delay of the feedback loop.

You can do the same analysis while counting DOWN.

Why are you using the 2N7000? Just use another inverter in the CD40106 package.
Why are you using -5V instead of GND?

 

This is a race condition, but one that is most likely not to be critical because of the handshaking aspect of the loop. But what is critical for this to work out is the difference between the actual time needed to reset the first latch to respond to MR and the time for the last latch to respond. More importantly, there is a glitching issue on the 4028 outputs that is much more likely to cause a problem.

For the race condition, consider that the minimum MR pulse width for reliable operation at 10 V is 300 ns. The manufacturer is saying that pulses shorter than this are not guaranteed to reset all four latches within the part. It may reset none of them or it may just reset some of them. There is no specification for the maximum skew between the first and the last flip flops resetting, which indicates that the manufacture is saying that you shouldn't design things such that this matters.

But let's look at the numbers to see what kind of differences might be needed to affect operation.

On the 40192, the propagation delay between MR and Q is typically 120 ns with a max of 240 ns.
On the 4028 the prop delay between input to output is typically 80 ns with a max of 160 ns.
I'd have to run some sims to estimate the prop delay for the transistor inverter, so instead I will use the typical and max values for the 40106, which are 70 ns and 140 ns, respectively. But this is only relevant to the LOAD signal, not the MR signal.

The fact that almost all of these specifications have the max at twice the typical implies that there is quite a bit of built in margin as far as the actual production limits are concerned, but we have no idea how much and thus shouldn't count on it.

From the time that the MR is asserted, it typically takes 120 ns to see the Q outputs change. From there it typically takes another 80 ns for the S4 output to change on the 4028, which is also the MR input. So, aside from prop delays associated with the routing and parasitics of the traces, your typical pulse width for MR is 200 ns, which is well short of the recommended 300 ns.

But, if all of the flip flops reset at about the same time, this should work. In fact, as long as the slowest one takes no more than 80 ns longer to respond than the fastest one, it will likely function properly. Given the symmetry of the reset logic within the counter, it is probably unlikely that there would be this much skew, but if there were, it would be well within spec. Even if the fasted flip flop was no faster than the typical, the slowest could be up to 120 ns slower and still be within spec. Aggravating this is if the 4028 is faster than typical, either because of manufacturing variances or possibly because of temperature differences. That reduces that max allowed skew from 80 ns to something smaller.

While is might be unlikely that the skew is enough to cause a problem, best practice is to ensure that the recommended minimum pulse width is met by adding delay elements, such as two of the 40106 inverters in series, in the MR signal.

The bigger problem is the potential for glitches on the outputs of the 4028. Each glitch will last roughly as long as the skew between sequential Q output changes and this could pretty easily be long enough for the counter to respond to them, at least partially. The best way to avoid this is to not use asynchronous inputs this way on sequential circuits.

 

Thank you gentlemen for the interesting comments.

@WBahn thanks for the analysis, the CD4028 decoding intermediate states wouldn't have occurred to me.

Firstly, you have a problem. The CD40192 counts UP on the rising edge while the DOWN input is HI.
Similarly, the UP input must be HI in order to count DOWN on the rising edge of DOWN. You need to fix that first.

Yes, I see. I wanted it to count on the button press, not on the de-press. But this won't work.

Why are you using the 2N7000? Just use another inverter in the CD40106 package.
Why are you using -5V instead of GND?

All CD40106 other devices are used up elsewhere. GND is used in other parts of the larger circuit.

I had also thought about adding delay elements in both feedback lines but thought of RC delays instead of 40106s in series. But

Each glitch will last roughly as long as the skew between sequential Q output changes and this could pretty easily be long enough for the counter to respond to them, at least partially. The best way to avoid this is to not use asynchronous inputs this way on sequential circuits.

that will only work if you make the delay really long?

Perhaps a better question then: how do you design this counting sequence (up-down with roll-over) is a synchronous way?

Edit:
If we start at count = 0 (S0 = 1) then Q3Q2Q1Q0 = DCBA = 0000.
We count down to 9 (S9 = 1) then DCBA = 1001.
Then we try to load 0011. Because C remains 0 this cannot S4->MR. It can glitch S0, S1, S2, S3 and S8 which we do not care about.
The only remaining problem is that D becomes 0 first and the load is incomplete. We may end up selecting S1.
For this we can add some RC from S9 to load. A maximum rise time for load is not specified so we won't ruin that.
But if we assume the same maximum rise time for count and load (5 us) you can probably still get away with an RC that satisfies that rise time and the minimum load hold time. So I suppose that part looks good.

Tomorrow I'll check the S4 -> MR loop to see if I can get away with that too.

Edit2:
In the case of S4 -> MR we go from

State DCBA
S4    0100
MR    0000

so the only glitch that can occur is that we reach the final state before the conversion is complete. So no problematic glitch can occur and probably not even a delay is needed. Then the circuit can be fixed by putting an appropriately sized capacitor in parallel with R11. And fix the counter inputs as noted by MrChips.

In the above edits the assumption is that a bit set to 0 that is going to be reset to 0 cannot glitch to 1. Does that seem about right @WBahn or have I missed the point?

 

Wbahn has certainly provided a whole lot of valuable analysis, quite A LOT OF VALUE!!, really.
My input is that CMOS timing is quite variable between brands of I.C. devices.
And unstated minimums are unstated for very good reasons. Reasons seldom given!!

The several comments are not only "interesting", they are valuable warnings. My own warning is that many of those parameters differ between different device manufacturers!!