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Hello! I'm studying computer engineering and there's a question in our logic circuits homework that I have solved but I'm not sure of my answers. I'd like to see if my answers are correct and reasonable.
This is the circuit and info on the propagation delays.
Clock frequency is 50 MHz
The question asks about the setup time and hold time needed for this circuit to work without violations.
My answer was as follows:
\[ t_{hold} \le t_{ccq}+t_{cd} \\ Upper FF: \\ t_{hold} \le t_{ccq} + t_{OR} + t_{NOT} + t_{AND} \\ t_{hold} \le 2+2+1+2 \\ t_{hold} \le 7ns\\ Lower FF:\\ t_{hold} \le t_{ccq} + t_{XOR} \\ t_{hold} \le 2+2 \\ t_{hold} \le 4ns\\ Min: t_{hold} \le 4ns \]
\[ t_{pcq}+t_{pd}+t_{setup} \le T\\ Upper FF:\\ t_{setup} \le T-(t_{pcq}+t_{pd})\\ t_{setup} \le 20-3-(5+2+5)\\ t_{setup} \le 5ns\\ Lower FF:\\ t_{setup} \le T-(t_{pcq}+t_{pd})\\ t_{setup} \le 20-3-7\\ t_{setup} \le 10ns\\ Min: t_{setup} \le 5ns \]
Is it correct? I've always had a little difficulty with setup and hold time.
This is the circuit and info on the propagation delays.
Clock frequency is 50 MHz
The question asks about the setup time and hold time needed for this circuit to work without violations.
My answer was as follows:
\[ t_{hold} \le t_{ccq}+t_{cd} \\ Upper FF: \\ t_{hold} \le t_{ccq} + t_{OR} + t_{NOT} + t_{AND} \\ t_{hold} \le 2+2+1+2 \\ t_{hold} \le 7ns\\ Lower FF:\\ t_{hold} \le t_{ccq} + t_{XOR} \\ t_{hold} \le 2+2 \\ t_{hold} \le 4ns\\ Min: t_{hold} \le 4ns \]
\[ t_{pcq}+t_{pd}+t_{setup} \le T\\ Upper FF:\\ t_{setup} \le T-(t_{pcq}+t_{pd})\\ t_{setup} \le 20-3-(5+2+5)\\ t_{setup} \le 5ns\\ Lower FF:\\ t_{setup} \le T-(t_{pcq}+t_{pd})\\ t_{setup} \le 20-3-7\\ t_{setup} \le 10ns\\ Min: t_{setup} \le 5ns \]
Is it correct? I've always had a little difficulty with setup and hold time.
