VHDL implementation - problem

zorro_phu · Feb 3, 2019

I have to implement the following diagram(attachment) in vhdl. When i run synthesis i get warning "[Synth 8-3917] design top_module" has port led3 driven by constant 0 but in the code i didn't connect led3 to be 0. i tried to solve it but no success. When i simulate, the outputs(led0,led1...led3) are always at 0. What i'm implementing is a state counter with control store and address jamming. In this implementation we have to use ic 74161,74244, and 74153.
74161 : http://users.ece.utexas.edu/~valvano/Datasheets/74LS163.pdf
74244 : http://www.sycelectronica.com.ar/semiconductores/74LS244.pdf
74153 : http://www.sycelectronica.com.ar/semiconductores/74LS153.pdf

The codes are as follows. Any help is greatly appreciated.

Code:

------------------------------------------------
IC 74161 Implementation
-----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ic74161 is
    port (
    CLR         : in std_logic; --Active Low
    CLK         : in std_logic;
    A,B,C,D     : in std_logic;
    QA,QB,QC,QD : out std_logic;
    ENP         : in std_logic;
    ENT         : in std_logic;
    LOAD        : in std_logic; --Active Low
    RCO         : out std_logic
    );
end ic74161;

architecture Behavioral of ic74161 is

    signal output : std_logic_vector(3 downto 0);
   
begin
    logic : process(CLK,CLR,ENP,ENT,LOAD)
    begin
        if(CLR = '0') then
            output<="0000";
       
        elsif(rising_edge(CLK)) then
            if(LOAD = '0') then --**start from here
                output(3) <= A;
                output(2) <= B;
                output(1) <= C;
                output(0) <= D;
            else   
                if(ENP = '1' and ENT = '1') then
                    output <= output + 1;
                else
                    output <= output;
                end if;
            end if;
        end if;
    end process logic;
    QA <= output(3);
    QB <= output(2);
    QC <= output(1);
    QD <= output(0);
   
    RippleCarryOut : process (output,ENT)
    begin
        if(output = B"1111" and ENT='1')then
            RCO <= '1';
        else
            RCO <= '0';
        end if;
    end process RippleCarryOut;
end Behavioral;

-----------------------------------------------
-----------------------------------------------
-----------------------------------------------

Code:

------------------------------------
IC74244 Implementation
-------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ic74244 is
    port(
    X1G,X2G             : in std_logic;
    X1A1,X1A2,X1A3,X1A4 : in std_logic;
    X2A1,X2A2,X2A3,X2A4 : in std_logic;
    Y1A1,Y1A2,Y1A3,Y1A4 : out std_logic;
    Y2A1,Y2A2,Y2A3,Y2A4 : out std_logic
    );
end ic74244;

architecture Behavioral of ic74244 is

    signal y1x1_output : std_logic;
    signal y1x2_output : std_logic;
    signal y1x3_output : std_logic;
    signal y1x4_output : std_logic;
    -------------------------------
    signal y2x1_output : std_logic;
    signal y2x2_output : std_logic;
    signal y2x3_output : std_logic;
    signal y2x4_output : std_logic;

   
begin
    X1 : process(X1G,X1A1,X1A2,X1A3,X1A4)
    begin
        if(X1G = '1') then
            y1x1_output <= 'Z';
            y1x2_output <= 'Z';
            y1x3_output <= 'Z';
            y1x4_output <= 'Z';
        else   
            y1x1_output<=X1A1;
            y1x2_output<=X1A2;
            y1x3_output<=X1A3;
            y1x4_output<=X1A4;
        end if;
    end process X1;
--------------------------------------------------------------
    X2 : process(X2G,X2A1,X2A2,X2A3,X2A4)
    begin
        if(X2G = '1') then
            y2x1_output <= 'Z';
            y2x2_output <= 'Z';
            y2x3_output <= 'Z';
            y2x4_output <= 'Z';
        else
            y2x1_output<=X2A1;
            y2x2_output<=X2A2;
            y2x3_output<=X2A3;
            y2x4_output<=X2A4;
        end if;
    end process X2;
    -----------------------------
    Y1A1 <= y1x1_output;
    Y1A2 <= y1x2_output;
    Y1A3 <= y1x3_output;
    Y1A4 <= y1x4_output;
    ------------------------------
    Y2A1 <= y2x1_output;
    Y2A2 <= y2x2_output;
    Y2A3 <= y2x3_output;
    Y2A4 <= y2x4_output;

end Behavioral;

-----------------------------------------------
-----------------------------------------------
-----------------------------------------------

Code:

------------------------------------------
IC74153 Implementation
------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ic74153 is
    --  Port ( );
    port(
    sel_A : in std_logic;
    sel_B : in std_logic;
    X1C1 : in std_logic;
    X1C2 : in std_logic;
    X1C3 : in std_logic;
    X1C4 : in std_logic;
    G1     : in std_logic;
    --Y1     : out std_logic;
    MPC_LOAD : out std_logic;
    bit9,bit10,bit12 : in std_logic
    );
end ic74153;

architecture Behavioral1 of ic74153 is
    signal output_y1 : std_logic;
    signal xor1 : std_logic;
    signal or1 : std_logic;
    signal temp_out : std_logic;
   
begin
    logic : process(G1,sel_A,sel_B,X1C1,X1C2,X1C3,X1C4)
    begin
        if( G1 = '1') then
            output_y1 <= '0';
        else
            case sel_A  is
                when '0'=>
                    case sel_B is
                        when '0'=>output_y1<=X1C1;
                        when'1'=>output_y1<=X1C2;
                        when others=>output_y1<='X';
                    end case;
                when '1'=>
                    case sel_B is
                        when '0'=>output_y1<=X1C3;
                        when '1'=>output_y1<=X1C4;
                        when others=>output_y1<='X';
                    end case;
                when others=>output_y1<='X';
            end case;
        end if;   
    end process;

    xor1<=output_y1 xor bit12;
    or1<= xor1 nor bit10;
    temp_out<=or1 nor bit9;
    MPC_LOAD<=temp_out;
end Behavioral1;

-----------------------------------------------
-----------------------------------------------
-----------------------------------------------

Code:

----------------------------------------
Control Store implementation
----------------------------------------
    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity control_store is

    Port ( 
    addr : in std_logic_vector(7 downto 0);
    data : out std_logic_vector(23  downto 0)
    );

end control_store;

architecture Behavioral of control_store is

begin
    process (addr)

    begin
    case addr is

    when X"00" => data <= X"000100";
    when X"01" => data <= X"020101";
    when X"02" => data <= X"040102";
    when X"03" => data <= X"060103";
    when X"04" => data <= X"081600";
    when others => data <= X"000100";

    end case;
    end process;
end Behavioral;

-----------------------------------------
Top Module
----------------------------------------

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top_module is
    port(
    CLK : in std_logic;
    PRESENT : in std_logic;
    JAM : in std_logic;
    sw0,sw1,sw2,sw3 : in std_logic;
    led0 : out std_logic;
    led1 : out std_logic;
    led2 : out std_logic;
    led3 : out std_logic
    );
end top_module;

architecture Behavioral of top_module is
    --COMPONENTS--
---------ic74161-------------------------------
    component ic74161 is
    port (
    CLR         : in std_logic; --Active Low
    CLK         : in std_logic;
    A,B,C,D     : in std_logic;
    QA,QB,QC,QD : out std_logic;
    ENP         : in std_logic;
    ENT         : in std_logic;
    LOAD        : in std_logic; --Active Low
    RCO         : out std_logic
    );
    end component;
---------74244----------------------------------
    component ic74244 is
    port(
    X1G,X2G             : in std_logic;
    X1A1,X1A2,X1A3,X1A4 : in std_logic;
    X2A1,X2A2,X2A3,X2A4 : in std_logic;
    Y1A1,Y1A2,Y1A3,Y1A4 : out std_logic;
    Y2A1,Y2A2,Y2A3,Y2A4 : out std_logic
    );
    end component;
--------74153------------------------------------
    component ic74153 is
    port(
    sel_A,sel_B : in std_logic;
    X1C1 : in std_logic;
    X1C2 : in std_logic;
    X1C3 : in std_logic;
    X1C4 : in std_logic;
    G1   : in std_logic;
    --Y1     : out std_logic
    bit9,bit10,bit12 : in std_logic;
    MPC_LOAD : out std_logic
    );
    end component;
---------control store-----------------------------
    component control_store is
    Port ( 
    addr : in std_logic_vector(7 downto 0);
    data : out std_logic_vector(23  downto 0)
    );
    end component;
----------Signal------------------------------------
    signal addr_top : std_logic_vector(7 downto 0);
    signal data_top : std_logic_vector(23 downto 0);
    signal mpc_load_temp : std_logic;
    signal RCO_ENT : std_logic;
    signal Q1_conn : std_logic_vector(3 downto 0);
    signal Q2_conn : std_logic_vector(3 downto 0);
    signal vcc : std_logic:='1';
    signal gnd : std_logic:='0';
begin
    instance1_74161 : ic74161 port map(
    CLK => CLK,
    CLR => PRESENT,
    ENT => vcc,
    ENP => data_top(8),
    LOAD => mpc_load_temp,
    ---------------
    A => data_top(0),
    B => data_top(1),
    C => data_top(2),
    D => data_top(3),
    ---------------
    QA => Q1_conn(0),
    QB => Q1_conn(1),
    QC => Q1_conn(2),
    QD => Q1_conn(3),
    ---------------
    RCO => RCO_ENT
    );
   
    instance2_74161 : ic74161 port map(
    CLK => CLK,
    CLR => PRESENT,
    ENT => RCO_ENT,
    ENP => data_top(8),
    LOAD => mpc_load_temp,
    ---------------
    A => data_top(4),
    B => data_top(5),
    C => data_top(6),
    D => data_top(7),
    ---------------
    QA => Q2_conn(0),
    QB => Q2_conn(1),
    QC => Q2_conn(2),
    QD => Q2_conn(3),
    ---------------
    RCO => open
    );
   
    instance_74244 : ic74244 port map(
    X1G => JAM,
    X2G => JAM,             
    X1A1 => Q1_conn(0),
    X1A2 => Q1_conn(1),
    X1A3 => Q1_conn(2),
    X1A4 => Q1_conn(3),
    ------------------- 
    X2A1 => Q2_conn(0),
    X2A2 => Q2_conn(1),
    X2A3 => Q2_conn(2),
    X2A4 => Q2_conn(3),
    ------------------- 
    Y1A1 => addr_top(4),
    Y1A2 => addr_top(5),
    Y1A3 => addr_top(6),
    Y1A4 => addr_top(7),
    ------------------ 
    Y2A1 => addr_top(0),
    Y2A2 => addr_top(1),
    Y2A3 => addr_top(2),
    Y2A4 => addr_top(3)
    );
   
    instance_74153 : ic74153 port map(
    sel_A => data_top(13),
    sel_B => data_top(14), 
    x1C1 => sw0,
    x1C2 => sw1,
    x1C3 => sw2,
    x1C4 => sw3,       
    G1 => gnd,
    bit9 => data_top(9),
    bit10 => data_top(10),
    bit12 => data_top(12),     
    MPC_LOAD => mpc_load_temp   
    );
   
    cont_store : control_store port map(
    addr => addr_top,
    data(16 downto 0) => data_top(16 downto 0),
    data(23 downto 21)=>data_top(23 downto 21),
    data(17)=>led0,
    data(18)=>led1,
    data(19)=>led2,
    data(20)=>led3
    );

    --------------------------------
--    led0<=data_top(17);
--    led1<=data_top(18);
--    led2<=data_top(19);
--    led3<=data_top(20);
    --------------------------------
end Behavioral;

Code:

--------------------------------------
Testbench
-------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity testbench is
--  Port ( );
end testbench;

architecture Behavioral of testbench is
   
    component top_module is
    port(
    CLK : in std_logic;
    PRESENT : in std_logic;
    JAM : in std_logic;
    sw0,sw1,sw2,sw3 : std_logic;
    led0,led1,led2,led3 : out std_logic
    );
    end component;
    --SIGNAL
    signal CLK : std_logic:='0';
    signal PRESENT : std_logic:='1';
    signal JAM : std_logic:='0';
    signal sw0,sw1,sw2,sw3 : std_logic;
    signal led0,led1,led2,led3 : std_logic;
   
begin
    uut : top_module port map(
    CLK => CLK,
    PRESENT => PRESENT,
    JAM => JAM,
    sw0 => sw0,
    sw1 => sw1,
    sw2 => sw2,
    sw3 => sw3,
    led0 => led0,
    led1 => led1,
    led2 => led2,
    led3 => led3
    );
   
    CLK <= not CLK after 100ns;

    sim1 : process
    begin
        sw0 <='0'; sw1 <='0'; sw2 <='0'; sw3 <='0';
        wait for 700 ns;
        sw0 <='0'; sw1 <='0'; sw2 <='0'; sw3 <='1';
        wait for 300ns;
        sw0 <='0'; sw1 <='0'; sw2 <='1'; sw3 <='0';
        wait for 300 ns;
        sw0 <='0'; sw1 <='0'; sw2 <='1'; sw3 <='1';
        wait for 300 ns;
        --------------------------------------------
        sw0 <='0'; sw1 <='1'; sw2 <='0'; sw3 <='0';
        wait for 300 ns;
        sw0 <='0'; sw1 <='1'; sw2 <='0'; sw3 <='1';
        wait for 300 ns;
        sw0 <='0'; sw1 <='1'; sw2 <='1'; sw3 <='0';
        wait for 300 ns;
        sw0 <='0'; sw1 <='1'; sw2 <='1'; sw3 <='1';
        wait for 300 ns;
        --------------------------------------------
        sw0 <='1'; sw1 <='0'; sw2 <='0'; sw3 <='0';
        wait for 300 ns;
        sw0 <='1'; sw1 <='0'; sw2 <='0'; sw3 <='1';
        wait for 300 ns;
        sw0 <='1'; sw1 <='0'; sw2 <='1'; sw3 <='0';
        wait for 300 ns;
        sw0 <='1'; sw1 <='0'; sw2 <='1'; sw3 <='1';
        wait for 300 ns;
        -------------------------------------------
        sw0 <='1'; sw1 <='1'; sw2 <='0'; sw3 <='0';
        wait for 300 ns;
        sw0 <='1'; sw1 <='1'; sw2 <='0'; sw3 <='1';
        wait for 300 ns;
        sw0 <='1'; sw1 <='1'; sw2 <='1'; sw3 <='0';
        wait for 300 ns;
        sw0 <='1'; sw1 <='1'; sw2 <='1'; sw3 <='1';
        wait for 300ns;

    end process;

end Behavioral;

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VHDL implementation - problem

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