ERROR in VHDL Code for FPGA(Spartan 3E) implementation of AES

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sakshi aneja

Joined Mar 5, 2012
1
This error is coming in our VHDL program code simulated in Xilinx 13.1
Please suggest a possible solution for this as soon as possible.I am enclosing the top module of my code in brackets


ERROR:pack:1107 - Pack was unable to combine the symbols listed below into a single IOB component because the site type selected is not compatible. The
component type is determined by the types of logic and the properties and
configuration of the logic it contains. In this case an IO component of type
IOB was chosen because the IO contains symbols and/or properties consistent with output or bi-directional usage and contains no other symbols or properties that require a more specific IO component type. Please double
check that the types of logic elements and all of their relevant properties
and configuration options are compatible with the physical site type of the
constraint
Rich (BB code):
(
-- 128bit AES Encryption Implementation
-- Contains device_level includes uController and Memory
-- Filename: device_level.vhd
library ieee;
use ieee.std_logic_1164.all;
use work.global.all;

entity DEVICELEVEL is
     port(  
		   clk:in std_logic;
		   resetn:in std_logic;
			--ps2 keyboard
		   ps2_data: inout std_logic;
		   ps2_clk: inout std_logic; 
			-- lcd
		   display_out: out std_logic_vector(7 downto 0);
		   nlcd_ena : out std_logic;
	--      loaddata: in std_logic;
 -- 	   loadencrypt: in std_logic;
--         loadkey : in std_logic;
	      lcd_rw :out std_logic;
	      lcd_rs : out std_logic;
			-- LED ASCII Keypress
		   leds: out std_logic_vector(7 downto 0));
end DEVICELEVEL;

architecture int_structure of DEVICELEVEL is
 signal     device_address_bus: std_logic_vector(10 downto 0);
 signal     device_rom_bus: std_logic_vector(7 downto 0);
 signal     device_ram_bus: std_logic_vector(15 downto 0);
 signal     device_opcode: std_logic_vector(3 downto 0);
 signal     device_status: std_logic_vector(2 downto 0);
 signal     inverse: std_logic;
 signal     int_loaddata,int_loadencrypt: std_logic;
 signal     rx_read, rx_data_ready, rx_released : std_logic;
 signal     rx_ascii : std_logic_vector(7 downto 0);
 signal     intLCD2Core : integer range 0 to 15;
 signal     Core2LCD : std_logic_vector(7 downto 0);
 signal     asciimode,inputaccept: std_logic;
 signal     loaddata,loadencrypt,loadkey:std_logic;
 signal     keypress: std_logic;

begin
 int_loaddata    <=  not loaddata    and inputaccept;
 int_loadencrypt <=  not loadencrypt and inputaccept;
 
CORE: AESCORE port map (opcode=>device_opcode,
                        inverse=>inverse,
			               rombus=>device_rom_bus,
		                  rambus=>device_ram_bus,
			               status_ext=>device_status,
                        address=>device_address_bus,
				            reset=>resetn,
			               clk=>clk,
			               rx_read=>rx_read,
		                 	rx_data_ready=>rx_data_ready,
			               rx_ascii=>rx_ascii,
			               rx_released=>rx_released,
								inputaccept=>inputaccept,
								asciimode=>asciimode,
			               leds  => leds,
								loaddata=>loaddata,
								loadkey=>loadkey,
								loadencrypt=>loadencrypt,
				            intLCD2Core=>intLCD2Core,
				            Core2LCD=>Core2LCD);
                        

CODE: PRGRMCNTRL port map (
			           status=>device_status,
                    reset=>resetn,
		              clk=>clk,
                    loadkey=>'0',
                    loaddata=>int_loaddata,
                    loadencrypt=>int_loadencrypt,
                    inverse=>inverse,
		              opcode=>device_opcode);	
										    		    
ROM: SBOX_ROM port map (
                      address=>device_address_bus(7 downto 0),
				          clk=>clk,
                      read=>device_address_bus(10),
                      inverse=>inverse,
                      output=>device_rom_bus);

RAM: KEY_RAM port map (
                      address=>device_address_bus(6 downto 0),
		                iobus=>device_ram_bus,
				          clk=>clk,
		                read=>device_address_bus(9),
   	                write=>device_address_bus(8),
		                enable=>resetn);

PS2: ps2_keyboard_interface 
  port map(
       clk => clk,
       resetn  =>resetn,
       ps2_clk => ps2_clk,
       ps2_data=>ps2_data,
      rx_data_ready=>rx_data_ready,
	  rx_read=>rx_read,
	  rx_ascii=>rx_ascii,
	  rx_released=>rx_released,
	   asciimode=>asciimode
     );

LCD: LCD_top port map (
             clk => clk,
             reset => resetn,
             display_out=>display_out,
             nlcd_ena =>nlcd_ena,
	          lcd_rw => lcd_rw,
	         lcd_rs =>lcd_rs,
	        opcode => device_opcode,
		   asciimode => asciimode,
		   keypress => rx_data_ready ,
			inputaccept=>inputaccept,
		       intLCD2Core=>intLCD2Core,
		       Core2LCD=>Core2LCD );



end int_structure;

)
 
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