You might be able to get by with only a few caps, but I wouldn't chance it.I ave heard that bypassing 74HC isn't strictly necessary apart from a few bypasses here and there. Is this true?
CMOS can generate some pretty high current spikes due to overlap current between the N and P MOSFETS when the output is changing states and you want to keep those from causing large voltage spikes on the V+ line.
It's essentially unlimited from a DC point of view.A second question is about fanout. Usually it's 10 LS loads per each 74HC cmos IC, however isn't it true that from 74HC to 74HC the fanout is virtually unlimited since CMOS takes so little current? So because I don't have a single LS in my design, only CMOS, then I don't really have to worry about fanout unless I am really connecting more than about 50 cmos loads to a single driver?
But each input adds its input capacitance and that slows the rise and fall times.
So you need to look at that with respect to the output drive current and the frequency of operation.
At some point the fanout could slow the rise/fall times to the point that the circuit operation is flaky.