Using Buffers to avoid trasmission line terminations?

Thread Starter

ComputerBuilder

Joined Oct 3, 2017
35
Hi friends,

I have a question about bus termination (transmission line theory).


I have been wondering if it is possible to solve the long line problem of needing termination resistors by splitting the wires in multiple bits by adding buffer IC's in between the parts. For example using 74HC244 buffers to split a long line so that the remaining lengths are so small that they don't need terminating resistors.

This seems to make sense to me because from what I understand the problem only occurs in between IC's.

Is this correct or wrong?

Is it possible that even by adding the buffers, that when they are open the line is still long? Or would this work?


Thanks a lot!
 

Thread Starter

ComputerBuilder

Joined Oct 3, 2017
35
It would work but it adds parts, power dissipation, and propagation delay, likely a poor trade-off just to avoid properly terminating the transmission line.

Good point.

How can I find the impedance of a transmission line? Let's say it's just a wire, would it be the plain resistance of the wire ?

My main problem is that I have a data bus and an address bus, and many devices use this bus so I am confused about how to terminate these buses.

In my case, I have an ALU which has its output into a data bus, and then many devices as inputs only. So to terminate this, would it be best to add resistors in series right at the ALU outputs, or could I also terminate it in parallel by adding the resistors anywhere on the bus, going to ground or Vcc?

I have another bus with many outputs instead of a single ALU output, and then this bus feeds into one of the ALU inputs. How then should I terminate this? Would it be at the ALU input in series? Or could I again terminate the bus anywhere in parallel with resistors to GND or VCC?

Thanks for your kind help.
 

crutschow

Joined Mar 14, 2008
23,379
How can I find the impedance of a transmission line? Let's say it's just a wire, would it be the plain resistance of the wire ?
No.
The characteristic impedance is related to how far the wire is from a ground so can by quite variable.
That's why transmission lines are designed to control the impedance by the conducting wire being a fixed distance from the ground, such as a coaxial cable or twisted wire pair.
On a PCB, microstrip or stripline layout is used to control the impedance.
an ALU which has its output into a data bus, and then many devices as inputs only. So to terminate this,....
Remember you are trying to control reflections from the end of the line, so the bus is terminated at the ends.
The energy of the signal is stored in the distributed LC of the line as it moves down the line. To absorb all this energy it must see a termination impedance at the end equal to the characteristic impedance.
If not, then the left over energy has no where to go and will be reflected back down the line.

If you are using single termination then the termination is at the far end in parallel to ground.
If using double termination then it is in series at the drive end and to ground at the far end.
The assumes that all the inputs are being tapped with a short enough connection from the transmission line to not significantly degrade the signal.
another bus with many outputs instead of a single ALU output, and then this bus feeds into one of the ALU inputs. How then should I terminate this?
All outputs need to be tri-state so that only one output is driving at a time.
With that, the termination rules are the same.
For double termination there would be a resistor in series with each tri-state output.
 

RichardO

Joined May 4, 2013
2,273
What is the speed of your bus and how long are the PCB traces? If the bus speed is only a few MHz and the traces are only a few inches you may not hae to terminate at all.
 

Thread Starter

ComputerBuilder

Joined Oct 3, 2017
35
There are no PCB traces. I am building this using wire wrap.

It's not very clear where the ends are because everything is daisy chained together.

Would the far end be the devices furthest away from the driver?
 

crutschow

Joined Mar 14, 2008
23,379
If the bus speed is only a few MHz and the traces are only a few inches you may not hae to terminate at all.
For digital signals it's the rise and fall time of the pulse edges that's the determining factor as to when transmission line effects become important, not the pulse frequency.
t's not very clear where the ends are because everything is daisy chained together.

Would the far end be the devices furthest away from the driver?
It would be the last wire-wrap in the chain, furthest away from the driver (which should be the start of the chain).

But what is he highest frequency and the estimated length of the chain?
 

Thread Starter

ComputerBuilder

Joined Oct 3, 2017
35
For digital signals it's the rise and fall time of the pulse edges that's the determining factor as to when transmission line effects become important, not the pulse frequency.
It would be the last wire-wrap in the chain, furthest away from the driver (which should be the start of the chain).

But what is he highest frequency and the estimated length of the chain?
So I am using the 74HC series of IC's. Then the longest length of wire will be around 30cm.

By the highest frequency do you mean my clock frequency or the highest frequency contained inside the edges of the signals?
 

crutschow

Joined Mar 14, 2008
23,379
If the highest clock frequency if 5MHz with a 200ns period, then the minimum signal pulse would be 100ns.
Assuming the wire propagation time is about 1/2 the speed of light, the time it takes the signal to travel 30cm is 30cm divided by 1.5e10cm/s = 2ns.
Since the rise and fall times of the 74HC series are about 7ns, the reflected wave will have only a small effect on the signal and will have plenty of time to settle before the pulse again changes state.

Below is the LT spice simulation of a 100Ω transmission line (likely reasonably close to your wirewrap wire impedance) with a 2ns propagation delay (separated into two 1ns lines in series).
The input generates a 100ns pulse with a 7ns rise-time and 30Ω output impedance as estimated from the 74HC00 data sheet.
Signal V(2) simulates a signal tap halfway down the line.
There is some slight overshoot and ringing but it's quite minor.

upload_2017-10-3_17-45-31.png
 

Thread Starter

ComputerBuilder

Joined Oct 3, 2017
35
What if the bus is not a straight line but is more like tree branches, diverting in various directions? Should all ends of all directions be terminated or is just one enough?
If the highest clock frequency if 5MHz with a 200ns period, then the minimum signal pulse would be 100ns.
Assuming the wire propagation time is about 1/2 the speed of light, the time it takes the signal to travel 30cm is 30cm divided by 1.5e10cm/s = 2ns.
Since the rise and fall times of the 74HC series are about 7ns, the reflected wave will have only a small effect on the signal and will have plenty of time to settle before the pulse again changes state.

Below is the LT spice simulation of a 100Ω transmission line (likely reasonably close to your wirewrap wire impedance) with a 2ns propagation delay (separated into two 1ns lines in series).
The input generates a 100ns pulse with a 7ns rise-time and 30Ω output impedance as estimated from the 74HC00 data sheet.
Signal V(2) simulates a signal tap halfway down the line.
There is some slight overshoot and ringing but it's quite minor.

View attachment 136427


My friend, thank you very much for taking the time to do this.

I am trying to understand how transmission lines work. From what I gather, if the signal edge is really slow, and the end of the bus is left floating for example, then the reflected wave has no effect on the signal at the driver, because the signal edge is so slow that when the reflected wave comes back, it only rings it a little bit but the signal is still rising (slowly) and so that doesn't matter.

The problem is when the signal edge is so fast that the wave front has no time to come back to the source sooner than the edge has risen, so that when the edge has risen to its final value, a big wave front starts going down the line, and this big wave reflects back and when it arrives at the source it doubles the value at the source (more or less), and causes a lot of high amplitude ringing, and this continues to ring as this big wave now at the source travels back into the output impedance of the driver, dividing itself as a voltage divider, and then causing further ringing with lesser amplitude until it settles.

Can I please ask something though. If the signal affected is an edge sensitive signal, for example, driving a counter, then this is really bad because the ringing can can further clocking of the counter. But if this signal is a level signal, then as long as it settles before the clock arises, everything is fine, because when the clock arises the signal will be at the correct level. So my question is, is it true that reflections are not relevant for non-edge-sensitive signals?
 

crutschow

Joined Mar 14, 2008
23,379
What if the bus is not a straight line but is more like tree branches, diverting in various directions? Should all ends of all directions be terminated or is just one enough?
If the branches are long enough to cause reflection problems, then you may have to terminate more than one.
But that forms a discontinuity at the junctions which can still cause a problem.
So you want to daisy chain the bus with only short branches along the way.
is it true that reflections are not relevant for non-edge-sensitive signals?
Only if the level has settled to within the tolerance of the desired logic state voltage when you look at the signal.
That's where the clock frequency enters the equation.
 

joeyd999

Joined Jun 6, 2011
4,244
Just FYI: if the timing can afford it, you can always slow the rise/fall times by adding a small cap to each of the the line driver outputs. This will decrease DC current but increase dynamic AC current.

I sometimes use this approach if I have one or two long lines that are toggled infrequently with sharp transitions.
 

RichardO

Joined May 4, 2013
2,273
Just FYI: if the timing can afford it, you can always slow the rise/fall times by adding a small cap to each of the the line driver outputs. This will decrease DC current but increase dynamic AC current.

I sometimes use this approach if I have one or two long lines that are toggled infrequently with sharp transitions.
Similarly, you can sometimes ac couple the terminator to reduce DC current needs.
 

Thread Starter

ComputerBuilder

Joined Oct 3, 2017
35
Here's a photo of my wire wrap board. It's a computer cpu built using 74HC and 181 ALU's.




As you can see it's small enough, however there will be another of these on top of this one, connected with a 50way ribbon cable, which I will keep as short as possible.


One thing Ive always wanted to know about termination is this: when a signal reflects back from an open end, back into the driver and through the output resistance, it then meets Vcc inside the driver's voltage source, and then does it proceed to GND or does it reflect back from Vcc into the transmission line again? And if so why does it reflect into the line again rather than going into GND ?
 
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