I am trying to understand how transmission lines work. From what I gather, if the signal edge is really slow, and the end of the bus is left floating for example, then the reflected wave has no effect on the signal at the driver, because the signal edge is so slow that when the reflected wave comes back, it only rings it a little bit but the signal is still rising (slowly) and so that doesn't matter.

There is a time/space calculation of energy flow on the length of transmission line and the energy stored on the transmission line during that energy flow. If the transmission line is electrically short at the frequency of the energy variations then you can usually treat the physical connections as a Lumped Element. This means in simple terms that if at any instant the difference in EM energy phase at any two points on the transmission line is negligible (electrically short), the time/space energy stored on the transmission line is negligible so transmission line effects will be negligible. In these cases damping resistors can be used to reduce ringing caused by the equivalent lumped element.

https://www.allaboutcircuits.com/te...nt/chpt-14/long-and-short-transmission-lines/

If the circuit in question handles low-frequency AC power, such short time delays introduced by a transmission line between when the AC source outputs a voltage peak and when the source “sees” that peak loaded by the terminating impedance (round-trip time for the incident wave to reach the line’s end and reflect back to the source) are of little consequence. Even though we know that signal magnitudes along the line’s length are not equal at any given time due to signal propagation at (nearly) the speed of light, the actual phase difference between start-of-line and end-of-line signals is negligible, because line-length propagations occur within a very small fraction of the AC waveform’s period. For all practical purposes, we can say that voltage along all respective points on a low-frequency, two-conductor line are equal and in-phase with each other at any given point in time.

In these cases, we can say that the transmission lines in question are electrically short, because their propagation effects are much quicker than the periods of the conducted signals. By contrast, an electrically long line is one where the propagation time is a large fraction or even a multiple of the signal period. A “long” line is generally considered to be one where the source’s signal waveform completes at least a quarter-cycle (90o of “rotation”) before the incident signal reaches line’s end. Up until this chapter in the Lessons In Electric Circuits book series, all connecting lines were assumed to be electrically short.

As transmission lines become electrically long then proper impedance matching becomes vital for signal integrity because of reflections.
https://www.allaboutcircuits.com/textbook/alternating-current/chpt-14/standing-waves-and-resonance/

 

As you can see it's small enough...

Ha ha. Yeah, for the 1960s.

Pretty though. Good job.

 

Ha ha. Yeah, for the 1960s.

Pretty though. Good job.

Since you like it, this is the beginning of the wrap, this board is gonna be extremely dense.

https://scontent-lht6-1.xx.fbcdn.ne...=09860f758ba5e9611e0e8f9a161927a3&oe=5A3CC203

 

One thing Ive always wanted to know about termination is this: when a signal reflects back from an open end, back into the driver and through the output resistance, it then meets Vcc inside the driver's voltage source, and then does it proceed to GND or does it reflect back from Vcc into the transmission line again? And if so why does it reflect into the line again rather than going into GND ?

Nice board.

A classic on transmission lines and reflections.

If you want to learn more I would recommend this old book.
https://www.abebooks.com/book-searc...lines-antennas-and-wave-guides/first-edition/

 

Nice board.

A classic on transmission lines and reflections.

If you want to learn more I would recommend this old book.
https://www.abebooks.com/book-searc...lines-antennas-and-wave-guides/first-edition/

I watched this video about 5 months ago haha! It's great indeed. Thanks for reminding me of it and sharing the book as well!

Best regards

CB

 

I been playing with the falstad simulator, and I've tried two kinds of termination.

The first kind has a resistor at the driver, and so a 5V pulse leaving the driver loads the resistor to 2.5v, and then a 2.5V pulse travels down the line. When it meets an open circuit, like a mosfet gate input, the pulse goes up to 5V, and then the 5V pulse travels back and is swallowed by the resistor at the driver which matches the line.

A second kind I tried is terminated at the receiver rather than the driver, and so this time a 5V pulse leaves the driver, then the end of the line goes to 5V when the pulse reaches there, and then is immediately swallowed by the resistor at the end.

What I do not understand is the reason why in the first case, why only 2.5V travels down the line rather than 5V ? Does the line and the matching resistor form a voltage divider? Why do they if the line's impedance is not really equal to the resistor in Ohms? I mean, the real impedance of the line is not its characteristic impedance is it? If it were I could see why they form a divider, but as far as I know it isn't.

I also tried terminating both the driver and the receiver, and again a 2.5V pulse travels down, rather than 1/3 of the voltage. Because it should also form a tripple divider in this case (in my mind), but clearly it doesn't.

If I have a resistor at the driver, the line, and same value res at the end, why isn't the pulse 5/3 = 1.66V instead of 2.5V?


Thanks for your help.

 

...why only 2.5V travels down the line rather than 5V ? Does the line and the matching resistor form a voltage divider? Why do they if the line's impedance is not really equal to the resistor in Ohms? I mean, the real impedance of the line is not its characteristic impedance is it?

But it is.
The combination of the line distributed series inductance and parallel capacitance appears as a resistance at high frequencies with a characteristic impedance determined by the L and C values.
But it doesn't dissipate the energy, it stores the energy in this inductance and capacitance with a value equal to what a resistor of the same resistance would dissipate.
So when you hit the line with a 5V pulse from a source with a series resistance equal to the line characteristic impedance you do get a voltage divider action that drops the voltage in half going down the line.

If I have a resistor at the driver, the line, and same value res at the end, why isn't the pulse 5/3 = 1.66V instead of 2.5V?

Because the line impedance is not dissipating any energy, it's just carrying the energy down the line. Thus it does not act as a voltage divider as if there were three resistors in series.
So when the 2.5V pulse of energy (equal to 2.5V across a resistor) hits the far end resistor of the characteristic impedance value, the energy is dissipated in the resistor, giving a pulse equal to the source end voltage.

If the resistor at the far end is not equal to the characteristic impedance then all the energy is not absorbed by the resistor and some of the energy is reflected back down the line.
It's sort of like the maximum power transfer theorem.
If the line and load impedances don't match, then the maximum power is not transferred.

That all make more sense now?

 

Because the line impedance is not dissipating any energy, it's just carrying the energy down the line. Thus it does not act as a voltage divider as if there were three resistors in series.
So when the 2.5V pulse of energy (equal to 2.5V across a resistor) hits the far end resistor of the characteristic impedance value, the energy is dissipated in the resistor, giving a pulse equal to the source end voltage.

You said it doesnt act like a triple divider when there is a resistor at the source and another at the far end (to GND), but then in the first case when there is just a resistor at the source and the line with open ends, you said they do form a divider. Now this has confused me. So why does it form a divider in the first case and not the second?

If the line simply transfers the energy, then in the first case, why doesn't all the energy gets dissipated in the first resistor? This is more confusing than I thought.

If the line does behave like a resistor, but doesn't dissipate the energy, then why is it that in the first case, with a single source resistor matching the line, why does the line actually seems like it is acting like a divider and "grabbing" 2.5V of the total 5V?

In the first case again I can see in the simulator that the voltage at the source resistor is 2.5V, and this pulse reaches the open end, and then becomes 5V. So maybe it becomes 5V exactly because the line doesnt consume it, so its still available at the end.

So in the second case then, the first resistor consumes 2.5V, then the line transfers the remaining 2.5V to the second resistor, but doesnt consujme anything itself. Maybe I get it now?

Yes it seems I can see why now.

So with two resistors, the 5V pulse leaves the source, divides itself immediatly between the two resistors, 2.5V each since they same value. But now there's another confusion because in the second case the line is not a divider, but in the first it is.

Does the voltage divide itself instantly in the second case between the two resistors? How does it know there is a second resistor at the end? It seems to know there is one, because only 2.5 drops at the source. Ok maybe it doesn't. Maybe the line does behave like a divider at first, and this is why only 2.5V drops at the source, and then the line transfers the energy to the second resistor and the second resistor takes 2.5V.

Suppose we terminate it both at the source and the end, and suppose not a pulse is sent, but suppose we set the voltage source from 0 to 5V and leave it at 5V. This splits into 2.5V at the first resistor, then the wave front starts going down the line, and the line forms a divider with the first resistor so that 2.5 drops at the line. Then the front reaches the second resistor and 2.5V drops at the second res. Both resistors then stay at 2.5V and the line is now at 0V. Theres no reflection and everything is settled.

Suppose the resistors are not matched, so that the source one is less than Z0 and the load resistor is more than Z0. What would happen?

Sending simply 5V down the line, would the first resistor drop a smaller voltage than the line, and then the smaller voltage on the line goes down the line and reaches the second resistor, but then since the second resistor is larger than both the source one and the line's Z0, a higher voltage would drop at the second resistor, my question is then, how does this happen? Because the source resistor would form a divider with the line and not with the second res, so how in the end does the second res drop more voltage than the line itself?

This is all extremely interesting and there is like you say a huge problem below everything in the physics. I think I am ignoring the fact that the line is built from C's and L's, but I'm trying to understand it on a higher level first, maybe this is a mistake.

 

I think my last question about different value resistors was naive. It then starts to get into wave theory actually doesnt it.

If the resistors are not matches then reflections will occurs of different signs.

I think I remember a formula, it was (Z + Z0) / (Z - Z0), or maybe the inverse of that I cant remember, which tells how much will reflect.

I think however that I want to understand the intuition behind it rather than rely on the formula.

I was running the simulator to see what happens and if the first resistor is smaller than Z0 and the second larger, then I could see that the first res forms a divider with the line perfectly at first, but then the pulse goes down the line and the line does not form a divider with the second resistor because I saw a higher voltage than 5V.

But of course it would because a higher valued resistor for the end one would imply a reflection of the same sign as the incident wave. And then we get into the fraction of reflections which the formula gives isn't it.

So basically the first resistor does form a divider instantly, and the remaining voltage is transferred by the line and reaches the second resistor, and it then is reflected like ping pong.

Am I on the right path ?

 

I did an experiment where I have a source resistance emulating a driver's output impedance, and then I terminated the line at the far end with the line's impedance, the problem is that the voltage at the far end, is not 5V but less, around 3V. But my logic should be at 5v. How can this be solved? If I increase the resistance of course there are more reflections.

Is the only solution in this case to terminate it at the driver serially? Can't I terminate this at the far end instead? What to do now?

 

I did an experiment where I have a source resistance emulating a driver's output impedance, and then I terminated the line at the far end with the line's impedance, the problem is that the voltage at the far end, is not 5V but less, around 3V. But my logic should be at 5v. How can this be solved? If I increase the resistance of course there are more reflections.

Is the only solution in this case to terminate it at the driver serially? Can't I terminate this at the far end instead? What to do now?

I understand the need to understand but you are making this far too complicated. Another book recommendation if you want to gain insight.
https://www.abebooks.com/servlet/SearchResults?isbn=9780750674034&n=100121503&cm_sp=plped-_-1-_-used
Chapter 8 is Transmission lines.
https://books.google.com/books?id=7...=TI digital system impedance matching&f=false

Which one looks more like your circuits transmission line.

A 100ft roll of 50 ohm coax or a 2ft wire pair?

calibrator specs
0.4 V ±1% into a 1-Mohm load,
0.2 V ±1.5% into a 50 ohm load,
or 8 mA ±1.5% into a short circuit.

1 MHz signal

Unterminated 100ft Coax waveforms using Tek2465 probe calibrator signal. Input signal on bottom, output signal on top.
Ugly reflections back to the source due to a open circuit impedance mismatch but the far signal still looks ok.

Unterminated 2ft wire pair. Ringing (very high frequency reflections) that can be cleaned up with standard logic signal terminations if needed.

http://web.cecs.pdx.edu/~greenwd/xmsnLine_notes.pdf
http://www.the-signal-and-power-int...te_Source_Termination_Resistor_Location_2.pdf

 

So basically the first resistor does form a divider instantly, and the remaining voltage is transferred by the line and reaches the second resistor, and it then is reflected like ping pong.
Am I on the right path ?

Yes, you are.
The line looks like a resistor with the characteristic line impedance but instead of consuming the energy, it stores it in the line inductance and capacitance as the pulse travels down the line.
At the far end this energy is transferred to the load resistance.
So it divides the voltage at the source, since energy is being transferred to the line.
At that far end there's no division because the energy is transferred back to a resistance.

But my logic should be at 5v. How can this be solved? If I increase the resistance of course there are more reflections.
Is the only solution in this case to terminate it at the driver serially? Can't I terminate this at the far end instead? What to do now?

If you use a driver with significant resistance compared to the line impedance than the only solution is to add a series resistance at the driver end to match the line impedance.

To terminate at the far end you will need a low impedance line driver (which are available) that can drive the line impedance to near 5V.

 

There are two equivalent ways to look at transmission lines.
1. As a distributed circuit of infinitesimal inductances and capacitances with parameters L and C
2. As a waveguide for signals with parameters v and Zo.

To the OP, keep your focus on the waveguide model (the models are interchangeable but some problems are easier with one model or the other) when you think about digital transmission line effects and reflections. One of the easiest ways to eliminate ringing/reflections is to reduce the slew rate of the output signal if you don't need the rise/fall time because of a slow(er) speed digital signal requirements like a 5MHz clock speed.
http://www.interfacebus.com/IC_Output_Slew_Rate.html

Diagrams from ELECTROMAGNETICS EXPLAINED

 

There are two equivalent ways to look at transmission lines.
1. As a distributed circuit of infinitesimal inductances and capacitances with parameters L and C
2. As a waveguide for signals with parameters v and Zo.

To the OP, keep your focus on the waveguide model (the models are interchangeable but some problems are easier with one model or the other) when you think about digital transmission line effects and reflections. One of the easiest ways to eliminate ringing/reflections is to reduce the slew rate of the output signal if you don't need the rise/fall time because of a slow(er) speed digital signal requirements like a 5MHz clock speed.
http://www.interfacebus.com/IC_Output_Slew_Rate.html

Diagrams from ELECTROMAGNETICS EXPLAINED

Those are some amazing and very clear and useful diagrams. Thank you very much for sharing them my friend. I will have a look at this course.

Thank you for the experiments as well.

The reason I am concerned was because as you can see on my profile photo, that was a computer I built from breadboards and jumpers, and the reflections on that were a monstrosity as I didn't terminate anything. This time I will be careful but then again the wires are much smaller on the wirewrap boards.

If I were to decrease the rise times of my signals, what would be the best to do? Could I put one capacitor in each line I need to decrease the rise/fall times of? Or is there a better way? I'll look at the attached document.

Thank you very much.

 

Yes, you are.
The line looks like a resistor with the characteristic line impedance but instead of consuming the energy, it stores it in the line inductance and capacitance as the pulse travels down the line.
At the far end this energy is transferred to the load resistance.
So it divides the voltage at the source, since energy is being transferred to the line.
At that far end there's no division because the energy is transferred back to a resistance.
If you use a driver with significant resistance compared to the line impedance than the only solution is to add a series resistance at the driver end to match the line impedance.

To terminate at the far end you will need a low impedance line driver (which are available) that can drive the line impedance to near 5V.

So I'll need low impedance drivers... I am using the 74HC244 for driving the needed outputs but I can't find their output Z on the datasheets. Are they coded in a language I can't understand or just not there? In any case, could I measure it by measuring the output current and using Ohm's law?

Thank you for all your wonderful help. I feel I have enough understanding now and I owe you to you guys I love this place!

 

It's not there. Normally the output current and fanout is listed for logic level buffers. (74HC244, Output current: 6 mA, devices have a fanout of 15 LS-TTL equivalent inputs per the datasheet) You then need to make a calculation of logic voltage levels, current and the needed resistance for that current for something close to impedance but TTL impedances are totally non-linear.

 

The reason I am concerned was because as you can see on my profile photo, that was a computer I built from breadboards and jumpers, and the reflections on that were a monstrosity as I didn't terminate anything. This time I will be careful but then again the wires are much smaller on the wirewrap boards.

If I were to decrease the rise times of my signals, what would be the best to do? Could I put one capacitor in each line I need to decrease the rise/fall times of? Or is there a better way? I'll look at the attached document.

Thank you very much.

Series resistors at the output of the drivers makes a defacto low-pass filter with wire to ground capacitance of the bus connections. This has the effect of decreasing the rise times of signals has it slows the rate circuit capacitance can be charged/discharged by the output drivers. As a few have said here wirewrap is old-school. Most of us have a few designs under the belt or have worked with it in the past. It's actually very forgiving at lower speed.
A wirewrap keepsake.

With TTL bypassing chips and good power decoupling is usually more important than reflections at clocked logic speeds below 10MHz with a proper vector type board.

 

Are they coded in a language I can't understand or just not there? In any case, could I measure it by measuring the output current and using Ohm's law?

It's not explicitly stated since that device is not normally used as a line driver and thus the output impedance is not of interest.
You can use this info from the data sheet:



You can estimate it from the difference between the supply voltage and output voltage divided by the output current.
Thus at for a supply of 4.5V at an output current of 6mA the difference is 4.5V - 3.98V = .52v / 6mA ≈ 87Ω.

You can also measure it by adding a known load and measuring the voltage.

But note that is impedance is not constant as the output goes from low to high and back.
For example, the voltage drop for sourcing a 6mA load (output high) at 4.5V supply is .52V but is only .26V to sink 6mA (output low).
So the output impedance approximately drops in half from high to low.
This means that an added series resistance will not match the transmission line impedance over the complete signal transition so you can't completely cancel all the reflections.
However you can likely do it sufficiently well for most digital line requirements, but it may require some experimentation to determine the optimum value.

 

Series resistors at the output of the drivers makes a defacto low-pass filter with wire to ground capacitance of the bus connections. This has the effect of decreasing the rise times of signals has it slows the rate circuit capacitance can be charged/discharged by the output drivers. As a few have said here wirewrap is old-school. Most of us have a few designs under the belt or have worked with it in the past. It's actually very forgiving at lower speed.
A wirewrap keepsake.

With TTL bypassing chips and good power decoupling is usually more important than reflections at clocked logic speeds below 10MHz with a proper vector type board.

Thank you. I have a few questions if I may.

I am actually using all CMOS rather than LS IC's. There isn't a single LS in my design. It's all 74HC which is all CMOS.

I ave heard that bypassing 74HC isn't strictly necessary apart from a few bypasses here and there. Is this true?

My wirewrap board is a little different. The V and G pins are below each IC, and it's impossible to put them below the IC's like a standard board.

I therefore decided to not put one bypass below each IC because of this. Is this a problem?

There's a solution by using IC sockets to lift the IC's and so there's space, but I destroyed one board trying to solder the caps directly and it melted V into G somehow and destroyed the board.

A second question is about fanout. Usually it's 10 LS loads per each 74HC cmos IC, however isn't it true that from 74HC to 74HC the fanout is virtually unlimited since CMOS takes so little current? So because I don't have a single LS in my design, only CMOS, then I don't really have to worry about fanout unless I am really connecting more than about 50 cmos loads to a single driver?

 

It's not explicitly stated since that device is not normally used as a line driver and thus the output impedance is not of interest.
You can use this info from the data sheet:
View attachment 136743
View attachment 136741

You can estimate it from the difference between the supply voltage and output voltage divided by the output current.
Thus at for a supply of 4.5V at an output current of 6mA the difference is 4.5V - 3.98V = .52v / 6mA ≈ 87Ω.

You can also measure it by adding a known load and measuring the voltage.

But note that is impedance is not constant as the output goes from low to high and back.
For example, the voltage drop for sourcing a 6mA load (output high) at 4.5V supply is .52V but is only .26V to sink 6mA (output low).
So the output impedance approximately drops in half from high to low.
This means that an added series resistance will not match the transmission line impedance over the complete signal transition so you can't completely cancel all the reflections.
However you can likely do it sufficiently well for most digital line requirements, but it may require some experimentation to determine the optimum value.

Thanks Crutschow.

But why is it Vcc - Voh divided by the current that gives the impedance? Why is it not simply the Voh? If the output voltage is the final logic level, then why isn't it simply the output voltage divided by the output current that gives the output impedance? Very surprising and I can't understand why.


Edit: is it because we are trying to calculate the internal impedance inside the IC and therefore we need the voltage difference inside the internal circuit and thefore it must be Vcc - Voh / I ?

If instead I put a load at the output, and knowing Vcc, and measuring the voltage across the load, and then using a voltage divider relation where R is output impedance and RL is the load, then finding R gives the output impedance?

My mind was away!