ELECTRONERD,

If you look at the specs, for the "Base-Emitter saturation voltage" on page two, you notice that it says "Ic=150mA, Vce=10V." Vce is calculated by the following equation: Vce = Vcc/Ve. So I made 5V at the emitter for my design with a 15V supply, 15V-5V=10V for Vce. You said:
Quote:
Originally Posted by Ratch
Yes, what about it?

So according to you, Vce shouldn't even be mentioned on the specs.

I don't know what you are trying to do. Vce = 10V is the pulse voltage used for the Vsat measurement. Where did you get Vce = Vcc/Ve from? What are you trying to say?

Ratch

 

ELECTRONERD,

I would think that it determines the gain of the transistor, but you've all said that gain isn't important for saturation.

No, I said that the beta is not related to the value of Vsat. You also asked about switching LED's and incorporating capacitors, which is off topic for this thread. Input means turning the base circuit on and off. I believe Audioguru answered your other question about where the load is located.

Ratch

 

vindicate,



Isn't 65 millivolts rather "near zero"?

The 2N2222 Vsat spec lists 0.3V and 1.0V for low and high current respectively. Isn't that close to zero too?

Ratch

Sorry I don't think I worded my question correctly. You said:

Sure there is. Remember what I said before? If both the emitter and collector diodes are forward biased, then saturation occurs. That is the cause, loss of Ic control with Ib is the effect. In a CE or CC configuration, all you have to do is figure what the total voltage drop across the emitter and collector resistance is. Then compare it to Vcc. If drop across the resistors is greater than Vcc, then you will have saturation because Vcc will not be able to maintain a reverse bias across the collector diode. Vsat is what the specs say it is, and there is nothing you can do about it except go or no-go into the saturation region.

That is where my example came in. You said that if the Vce Drop is greater than Vcc you will be in saturation. But in my example Vcc is 10V and Vce is 65mV. And 65mV is not greater than 10V.

 

ELECTRONERD,



I don't know what you are trying to do. Vce = 10V is the pulse voltage used for the Vsat measurement. Where did you get Vce = Vcc/Ve from? What are you trying to say?

Ratch

Oops, I meant that Vce = Vcc - Ve. What I don't understand is that on the 2N3904 datasheet they don't even bother to list Vce (like in the PN2222 they say Vce = 10V), instead they have what Ic and Ib should be, but the PN2222 doesn't list what Ib should be.

 

vindicate,

Quote: by Ratch
Sure there is. Remember what I said before? If both the emitter and collector diodes are forward biased, then saturation occurs. That is the cause, loss of Ic control with Ib is the effect. In a CE or CC configuration, all you have to do is figure what the total voltage drop across the emitter and collector resistance is. Then compare it to Vcc. If drop across the resistors is greater than Vcc, then you will have saturation because Vcc will not be able to maintain a reverse bias across the collector diode. Vsat is what the specs say it is, and there is nothing you can do about it except go or no-go into the saturation region.

Quote by vindicate: That is where my example came in. You said that if the Vce Drop is greater than Vcc you will be in saturation. But in my example Vcc is 10V and Vce is 65mV. And 65mV is not greater than 10V.

If you are referring to my quote you just posted, I never made such a statement. I said that if the total voltage drop across the emitter and collector resistors is greater than Vcc, then saturation will occur. Read it again. I never said to compare it Vce.

OK, let's look at your example. The voltage at the collector is 0.06531V . The voltage at the base is 0.69278V . Therefore the collector diode is forward biased, which along with the forward biased emitter diode makes the transistor saturate. As you can see, almost all the 10V Vcc is dropped across the collector resistor. There is not enough Vcc left to reverse bias the collector into the active region, so the transistor saturates.

Ratch

 

ELECTRONERD,

Oops, I meant that Vce = Vcc - Ve. What I don't understand is that on the 2N3904 datasheet they don't even bother to list Vce (like in the PN2222 they say Vce = 10V), instead they have what Ic and Ib should be, but the PN2222 doesn't list what Ib should be.

Actually, it should be Vce = Vcc -Vemitter-resistor - Vcollector-resistor.

I would surmise that since a 2N2222 can handle 5 times the current of a 2N3904, they use a pulse measurement of 10V Vce for the heavier duty transistors. Remember, this 10 volts is the setup voltage and not the Vsat voltage. The values of Vsat are shown at a lower and higher current. The higher current shows a higher Vsat voltage probably because of the bulk resistance of the semiconductor and the contact resistance.

 

on a PN2222A the min saturation voltage is 0.6volts. So does the mean if the voltage on base is .6V it's fully on? As in no restriction in current through C-E?

Also what happens when you go over the B-E Satuarion Max? According the the PN2222A datasheet the max is 1.2 or 2V depending on Ic.

I am so glad you asked this. You are correct in supposing that the saturation voltage is dependent on the CE. You can easily demonstrate this by changing the collector load resistance. The lower that resistance, the greater voltage necessary for saturation.

This is particularly important when you start moving away from the "small signal" model toward actual power transistors. There's a LOT more interaction between input and output parameters under these conditions!

Eric

 

vindicate,

If you are referring to my quote you just posted, I never made such a statement. I said that if the total voltage drop across the emitter and collector resistors is greater than Vcc, then saturation will occur. Read it again. I never said to compare it Vce.

OK, let's look at your example. The voltage at the collector is 0.06531V . The voltage at the base is 0.69278V . Therefore the collector diode is forward biased, which along with the forward biased emitter diode makes the transistor saturate. As you can see, almost all the 10V Vcc is dropped across the collector resistor. There is not enough Vcc left to reverse bias the collector into the active region, so the transistor saturates.

Ratch

I thought you meant the resistance inside the transistor, as in the resistance of of CE. So what you were referring to is any external resistance connected to the collector and emitter? Correct?

 

vindicate,



Good question. If you look at the parameter column, you will see a asterisk. Following the asterisk to the bottom you will see that they are using a 10V pulse voltage with a specified width and duty cycle. Averaged out, it probably comes out to the value in the max column.

Ratch

Hey,
Its something which I didnt qutie understand myself.

1. First, how do they force IC to be once 500mA and the other time 150mA?

2. Second, if VCE is a <2% (duty cycle) 10V pulse, then it can average to a maximum value of 2% * 10V = 0.2V. So how come they claim VCEsat (which you defined as the average value of the pulse) to be once 0.3V (max) and in the second time 1V (max)?

Thank you very much.

 

Whose datasheet for the PN2222A wrongly shows a Vce of 10V when the transistor is saturated?

I looked at 25 datasheets that did not say that.

 

Audioguru,
Are you refering to me?
I didnt say that VCE sat equals 10V, I said that according to Ratch, VCE sat is the average of the <2% (d.c.) 10V pulse, and was wondering how did it turn out to be once 0.3V and in other time 1V?

At all, I'd expect the average value of such pulse to be max 2% * 10V = 0.2V.

 

vindicate,

I thought you meant the resistance inside the transistor, as in the resistance of of CE. So what you were referring to is any external resistance connected to the collector and emitter? Correct?

You did not quote me on what statement you were talking about, so I cannot answer you. However, you should realize that whenever Ic exists in a resistance such as the emitter and collector resistances, it subtracts voltage from Vcc which is needed to reverse bias the collector diode.

Ratch

 

alphacat,

First, how do they force IC to be once 500mA and the other time 150mA?

By selecting the collector resistor to limit the current to whatever value they want at the designated Vcc.

Second, if VCE is a <2% (duty cycle) 10V pulse, then it can average to a maximum value of 2% * 10V = 0.2V. So how come they claim VCEsat (which you defined as the average value of the pulse) to be once 0.3V (max) and in the second time 1V (max)?

I do not know the protocols the testing engineers used to measure those values. I believe I said in post #33 that it "probably" is the average. I did not mean the average of 2% of 10V. There is no variation in that. I meant the average of the measured voltage over the full duty cycle. That will vary with each transistor. Perhaps you would like to look up the JEDEC specifications on how saturation voltage is measured? The higher saturation voltage, 1.0V was measured for the higher current. I gave a plausible explanation for that in post #46.

Ratch

 

Ratch,
Thank you very much for helping out.

I read your #46 post, and your last post.
If VCE is a <2% 10V pulse, then wouldnt the measured CE voltage be identical to the pulse?
Therefore i dont quite understand how come they received to different average values - 0.3V and 1V - for the same pulse.

 

alphacat,

If VCE is a <2% 10V pulse, then wouldnt the measured CE voltage be identical to the pulse?

No, the other 98% of the time the voltage is much less than 10V, so the average voltage was much less than 10V. Do you know what an average is?

Therefore i dont quite understand how come they received to different average values - 0.3V and 1V - for the same pulse.

Because the measured average voltage was higher during 98% of the time when a higher current (500ma) existed in the transistor.

Ratch

 

vindicate,



You did not quote me on what statement you were talking about, so I cannot answer you. However, you should realize that whenever Ic exists in a resistance such as the emitter and collector resistances, it subtracts voltage from Vcc which is needed to reverse bias the collector diode.

Ratch

Here is what I'm referring to:

Sure there is. Remember what I said before? If both the emitter and collector diodes are forward biased, then saturation occurs. That is the cause, loss of Ic control with Ib is the effect. In a CE or CC configuration, all you have to do is figure what the total voltage drop across the emitter and collector resistance is. Then compare it to Vcc. If drop across the resistors is greater than Vcc, then you will have saturation because Vcc will not be able to maintain a reverse bias across the collector diode. Vsat is what the specs say it is, and there is nothing you can do about it except go or no-go into the saturation region.

So my question is:

When you say voltage drop across the emitter and collector resistance do you mean the resistance of the actually Collector-emitter junction or do you mean all external resistance connected to the Collector and emitter?

To figure out the Vdrop across all resistance(and have it be higher than VCC) you would need to know HFE though wouldn't you?
In order to figure the Vdrop though, you would need to

 

vindicate,

When you say voltage drop across the emitter and collector resistance do you mean the resistance of the actually Collector-emitter junction or do you mean all external resistance connected to the Collector and emitter?

I mean the later, the external resistors Re and Rc.

To figure out the Vdrop across all resistance(and have it be higher than VCC) you would need to know HFE though wouldn't you?

You need Ie for Re and Ic for Rc. How you get Ie and Ic is up to you. Ie and Ic are usually about the same. If you know Hfe is high enough, then you can estimate Ie from the feedback principle. "Higher than Vcc" for saturation to occur, yes?

In order to figure the Vdrop though, you would need to

What?

Ratch

 

You cannot figure the saturation voltage loss because each transistor is different. Simply feed it the amount of base current that is shown on the datasheet (1/10th of the collector current for most little transistors) and a good one will have a typical voltage loss and a poor but passing one will have the spec'd max voltage loss.

 

alphacat,



No, the other 98% of the time the voltage is much less than 10V, so the average voltage was much less than 10V. Do you know what an average is?



Because the measured average voltage was higher during 98% of the time when a higher current (500ma) existed in the transistor.

Ratch

Hey,
thanks again for the help.

I don't understand something.
The engineers who test the transistor are the ones who determine the exact spec of the pulse.
This pulse is applied on the CE junction, right?
So they actually forcing VCE to be equal whatever pulse they set up.

Is this how they test VCEsat?
According to the duck, the base current should be 1/10th of the collector current.

 

alphacat,

The engineers who test the transistor are the ones who determine the exact spec of the pulse.

Is that a question? If so, it deserves a question mark. The last time I knew about it, the Joint Electron Device Engineering Council (JEDEC) specified the test methods. See http://en.wikipedia.org/wiki/JEDEC and http://www.jedec.org/ .

This pulse is applied on the CE junction, right?
So they actually forcing VCE to be equal whatever pulse they set up.

I would be guessing if I said yes. Check with JEDEC or the manufacturer to find out for sure.

Is this how they test VCEsat?

Or perhaps they pulse Vcc. Who knows?

According to the duck, the base current should be 1/10th of the collector current.

I believe he is quoting a rule of thumb that says Ib should be 1/10 of Ic to insure saturation. That is not part of the test standard. It is a design technique.

Ratch