Hi all
I was dimensioning the CE capacitor. To do that I was looking at some formulas seen in class. I wanted to compare such capacitor with the one proposed by Jony130. The formula (freq_C=1/(2*pi*Req*C) ) involves the knowledge of the loop gain (open loop gain*beta). It appears to be negative in my schematic. What does it mean? Is something wrong? In a different exercise in class I got a positive number: I though positive numbers were to be expected.

 

It looks like current mirror Q6 saturates and Q2 and Q4 are turn off. I'm not sure why though. I have to change R5 to 4.7k as previously suggested me with the complete schematic.

 

What can I say? Once again you break the DC negative feedback loop. And in this amplifier, this loop is responsible for setting the proper DC operating point. So what have you expected?

And by "CE capacitor" you meant a dominant pole compensation capacitor (miller compensation capacitor)? Or what?

 

And by "CE capacitor" you meant a dominant pole compensation capacitor (miller compensation capacitor)? Or what?

Exactly. I've seen that method to obtain loop gain (detach the feedback and ground negative input) but I've read in another forum that there's even another method to obtain that value without having to open the feedback loop. Which method I don't know though.

 

And som info about bootstrapping
https://forum.allaboutcircuits.com/...o-amplifier-calculations.160221/#post-1397602

 

Again, the parts are so far apart in your simulation that the text cannot be seen.

 

@Audioguru again Do you use a smartphone to read the schematics? I'm just curious because you are the only one that points out this issue...

 

Here you have a simulation file so you can plot the oop gain (Aol* Feedback factor). Just plot this expression

-1/(1-1/(2*(I(Vi)@1*V(x)@2-V(x)@1*I(Vi)@2)+V(x)@1+I(Vi)@2))

As for the miller compensation capacitor Cm. This capacitor has an influence on unit gain frequency as well as on slew rate. SR ≈ Ic10/Cm (input stage collector current).
And we can find Cm capacitor value using this equation
C = 1/(2 * pi * FT * 2*re * Acl) ≈ 0.16/( FT*2*re*Acl)

Where:
FT - unity gain crossover frequency
re - 26mV/Ic ----> Ic - input stage collector current.
Acl - Close loop voltage gain (1 + R12/R13 = 1+ 22kΩ/0.27kΩ = 82 V/V)

For example, if I choose FT = 200kHz we have Cm = 0.16/(200kHz * 82 * 52Ω) = 180pF. And SR = 1mA/180pF = 5.6V/μS

 

Thanks a lot for the detailed reply. I will look at it in a few minutes.
I was looking at phase margine and gain margine of the circuit... Maybe I'm doing some mistake but it looks like they are +90.8deg and -37.8dB... Aren't these values alone sufficient to say that my circuit is stable? However it looks like I need a miller compensation capacitor since I've got peaking right?

 

I guess I am the only person who notices that the parts on your simulation are so far apart that the text cannot be seen.
My computer monitor screen is 23" or 59cm diagonal.
Here is where I reduced the spaces between most of the parts and it can be seen much better:

 

The peaking shows that with negative feedback added then the amplifier will oscillate.
Then a frequency compensation capacitor (Miller) is needed.
But then the closed loop frequency response will cut high audio frequencies because the open loop frequency response
is already limited by something, the 2N3055 transistor that was used 55 years ago?

 

Maybe I'm doing some mistake but it looks like they are +90.8deg and -37.8dB.

This is a typical example of a GIGO. Who told you that this is the right way to do?

 

This is a typical example of a GIGO. Who told you that this is the right way to do?

Well... it was the professor that told me to do that... a young professor... something wrong?
What does GIGO stands for?

 

Well... it was the professor that told me to do that... a young professor... something wrong?

Really? He gives you the idea that you can break the negative feedback loop? And do something like this:
https://forum.allaboutcircuits.com/attachments/pm-gm-png.196340/

Here you have another correct method of finding the loop gain (simulation file).
Plot the Vout to get the loop gain.

What does GIGO stands for?

Garbage In, Garbage Out

 

I have added the compensation capacitor. It looks like the circuit satisfies the project requirements even without C1=470 uF.
What was that capacitor for? In class we haven't even seen a capacitor in that position.
Now i'm gonna write the method that I used to design the compensation capacitor ( I got a value way bigger than yours) so that you can tell me what you think about it.

 

Here there is the method that I've seen in class to choose the capacitor size. Maybe the resulting size is way too big.
https://www.dropbox.com/s/cs9zzeoxh1octbg/compensation.docx?dl=0

 

What was that capacitor for?

This capacitor as every capacitor does blocking the DC voltage. What RF1 and RF2 do in the circuit?

Here there is the method that I've seen in class to choose the capacitor size. Maybe the resulting size is way too big.
https://www.dropbox.com/s/cs9zzeoxh1octbg/compensation.docx?dl=0

LOL. The loop gain will be much large then this 12.44dB.

The input stage gain is Av1 ≈ ( 680Ω||300*7Ω )/52Ω = 9 V/V and the VAS gain Av2 = 3k V/V and the output stage gain 0.9V/V (I'm guessing here) we have:
AOL = 9 * 3k * 0.9 = 24 000 V/V = 87dB (simulation shows 85dB)

 

So is the method I have shown completely wrong? Can it be a rough approximation? Maybe in some cases? I ask just because it looks strange to me that I was told to follow a completely wrong method...

C = 1/(2 * pi * FT * 2*re * Acl) ≈ 0.16/( FT*2*re*Acl)
Where:
FT - unity gain crossover frequency
re - 26mV/Ic ----> Ic - input stage collector current.
Acl - Close loop voltage gain (1 + R12/R13 = 1+ 22kΩ/0.27kΩ = 82 V/V)
For example, if I choose FT = 200kHz we have Cm = 0.16/(200kHz * 82 * 52Ω) = 180pF. And SR = 1mA/180pF = 5.6V/μS

Is there a reference for this formula?
thanks

 

This capacitor as every capacitor does blocking the DC voltage. What RF1 and RF2 do in the circuit?

Those are feedback resistors. Don't the set the closed loop gain? Why do I have to block that DC voltage? Does it wreck the amplifier performances in some way?

 

So is the method I have shown completely wrong?

The method you used to find the loop gain is completely wrong.

Is there a reference for this formula?

Unfortunately not. Unfortunately not. But if you understand how the Cm capacitor affects the voltage gain of an input stage + VAS stage. It should be easy.
Notice that we want to set the unity gain (1 V/V = 0dB) at the crossover frequency (when AOL = ACL ). And the gain of an input stage and the VAS stage will become equal to X_Cm/(2re) (at high frequency).

Those are feedback resistors. Don't the set the closed loop gain? Why do I have to block that DC voltage? Does it wreck the amplifier performances in some way?

How this capacitor affects the amplifier voltage gain (ACL)?