The quiescent current of the input stage is select based on Q8 base current (VAS stage - Voltage Amplifier Stage).
Since the input and the VAS work in class A we need to choose I_input_stage >> I_vas.
But in this case, I just pick a nice round number IcQ10 = 1mA.

In this procedure it's not considered the signal swing. Shouldn't I check that the maximum voltage swing is allowed in every stage?
In the mentioned link:
https://forum.allaboutcircuits.com/...ign-basic-questions.104719/page-6#post-804580
A formula is used to find the current in differential branches:
ICQ1 = 10 * ICQ3/Hfe_min = 10 * 20mA/100 = 2mA
Is even this formula a rule of thumb formula?

 

ok... in post #95... I meant to get rid of C2 cap.

To make a fully DC coupled amp, you would also need to short out C1.

 

When you project an amplifier like this one, what's the order of actions you follow? Do you project one stage after the other? I propose again a question that for me is very important: In the procedure aforementioned it's not considered the signal swing if I'm not wrong. Shouldn't I check that the maximum voltage swing is allowed in every stage?

 

Some light reading: https://epdf.pub/download/audio-power-amplifier-design-handbook.html

 

In this procedure it's not considered the signal swing. Shouldn't I check that the maximum voltage swing is allowed in every stage?

If design properly the maximum output swing is determined by the output stage and a VAS stage Vce saturation voltage.

The situation will look like this:

The positive clipping voltage:


Vo_+max = Vcc - Vce(min) - 2Vbe or if T3 do not provide enough current we will have
Vo_+max = ( β1 * β2 ) * Ic3 * RL

And the negative clipping voltage:



Vo_-max = Vee - 2Vbe - Vce(sat)

And typically at high collector current the Vbe voltage will be larger than 0.6V as we typically assume.

A formula is used to find the current in differential branches:
ICQ1 = 10 * ICQ3/Hfe_min = 10 * 20mA/100 = 2mA
Is even this formula a rule of thumb formula?

No, because except the output stage all other amplifier stages works in class A, so to minimize the THD produced by a class A stages we want the AC collector current component to be as small as possible compere the DC component (quiescent current).

As a side note.
I know that is is very common for the "beginners" to look for the "formula" for everything.
But you don't find "formula" for every component in the circuit the Lvw put it nicely:

It would be a very simple task to design an amplifier stage if you would have formulas for every single component. Even a schoolboy could do it.
Thus, please realize that in the case of circuit ANALYSIS you have one single solution only.
On the contrary, for circuit DESIGN - in principle - there is an infinite number of "solutions". Here, "solution" means:
One of several circuit alternatives that are able to meet your requirements. This explains why you have to choose some parts values and parameters.
And this makes that circuit design is a really challenging task:
To find the "best" solution as a trade-off between several (often conflicting) requirements (technical, economical, reliability, ..)

And some good bedtime reading:
http://www.kennethkuhn.com/students/ee351/power_amplifier1.pdf

 

The positive clipping voltage:
View attachment 196032

Vo_+max = Vcc - Vce(min) - 2Vbe or if T3 do not provide enough current we will have
Vo_+max = ( β1 * β2 ) * Ic3 * RL

And the negative clipping voltage:

View attachment 196034

Vo_-max = Vee - 2Vbe - Vce(sat)

T3 doesn't provide enough current for what? Why does the formula change?

I should check voltage swing even in the other 2 stages, right? They are so small that they have enough headroom tho.

 

In the formula: ICQ1 = 10 * ICQ3/Hfe_min = 10 * 20mA/100 = 2mA
Why 10? Why not 5?

 

T3 doesn't provide enough current for what? Why does the formula change?

For example when the output stage does not have enough current gain then the voltage clipping will acquire early than T3 enters saturation.

I should check voltage swing even in the other 2 stages, right? They are so small that they have enough headroom tho.

There is no such need if properly design I_c_quiescent >> I_c_ac_component

In the formula: ICQ1 = 10 * ICQ3/Hfe_min = 10 * 20mA/100 = 2mA
Why 10? Why not 5?

Because 10 is an order of magnitude. Nothing magical happens there.
If you want you can calculate the "error" if you use 5 instead of 10 or 100 for comparison.

But to simplify it suppose we have 10V battery with the source resistance Rs = 100Ω. And now we will connect a load resistance to the circuit.
RL = 5*Rs = 500Ω
RL = 10*Rs = 1kΩ
RL = 100Rs = 10kΩ
And this is what we get (Ideally we want VL = 10V):



Notice how "error" is changing.

 

Regarding the first answer... 0.14mA ?In such a current mirror shouldn't I always have 3mA? Your answer may also answer to the question that I have regarding my current mirror. I was expecting (16-0.65)V/3300ohm=4.65mA current from the mirror but I obtained 5.24mA... strange...

 

Regarding the first answer... 0.14mA ?In such a current mirror shouldn't I always have 3mA?

No. You will get 3mA as long as T3 dos not saturated. In saturation, T3 will no longer "produce" 3mA.
Open the attached sim file.

I was expecting (16-0.65)V/3300ohm=4.65mA current from the mirror but I obtained 5.24mA... strange..

Did you ever hear about the Early effect?
To fix it add emitter resistors into the current mirror (see the file).

 

I greatly appreciate your help. It's amazing how patient you are... In order to have T2 saturated souldn't be BE and BC forward biased, which means Vb>Ve & Vb>Vc? It happens when too much current flows into its base right?

 

In order to have T2 saturated souldn't be BE and BC forward biased,

Yes, in saturation both BJT junction conduct a current.

It happens when too much current flows into its base right?

Well, it depends on which side you are looking at the situation.

Try to find Ic and Vce in case B and C



And notice that in all of these cases the base current is unchanged.

 

Yes, in saturation both BJT junction conduct a current.

In your simulation I don't get why T2 collector voltage > T2 base voltage if T2 saturates...

 

T2 ??

 

T2 ??

Q2 2N3055 sorry

 

O I see I made an error it should be:

No. You will get 3mA as long as T3 dos not saturated. In saturation, T3 will no longer "produce" 3mA.
Open the attached simulation file (current_mirror_sat.asc #110).

 

Maybe I got it right now. Vb>Ve & Vb>Vc relation is for npn bjt saturation BUT Q3b in your mirror simulation is pnp so that relation becomes Vb<Ve & Vb<Vc, right?
And I've done my homowork and I've seen that only C circuit saturates.

 

BUT Q3b in your mirror simulation is pnp so that relation becomes Vb<Ve & Vb<Vc, right?

Right.

And I've done my homowork and I've seen that only C circuit saturates.

But do you understand why?

 

But do you understand why?

Well, I've noticed that the collector voltage is lower that the base voltage, so the saturation relation that I've written above is satisfied. Maybe you wanted to hear something more interesting though...

 

An audio amplifier should avoid any of its transistors having saturation because saturation causes clipping distortion.
Even having only a little saturation is bad because during saturation then the negative feedback is eliminated for that moment resulting in distortion much more than you think.

An audio amplifier should have power headroom (extra power available) so that it never has clipping.
Sounds produced by rock bands are different. They use effects to produce as much distortion as they can, then they cannot hear if the amplifier is clipping or not so it is usually turned up too high and produces clipping.