I am trying to simulate synchronous 3 bit counter as the page below but couldn't get the right result.
http://www.zeepedia.com/read.php?d_flip-flop_based_implementation_digital_logic_design&b=9&c=32
Could anyone check why Q1 and Q2 are zero here?

 

Why have you let so many inputs floating?

 

Why have you let so many inputs floating?

I try the asynchronous with these pins floating and had no problem. So I didn't connect these pins to ground.
P.S: I've just tried to connect unused pins to ground but the same problem.

 

Just connecting unused pins to ground may not do what you want. What happens with an AND gate when any pin is connected to ground?

What are the pins on the side of the logic gates for?

 

What method did you use to design this? Why isn't the output of A1 connected to any other flip-flop but A1?

 

Anhnha, your clock is correct, but the interconnects among the flip flops are a mess.
Think about how A2 needs to know the state of A1 to do its job right. See if that helps.

Oh, and don't ground those unused inputs, that would be bad. Think pull-ups.

 

What method did you use to design this? Why isn't the output of A1 connected to any other flip-flop but A1?

Probably because it's the msb. Note that the lsb is free-running and the other two either hold their value or toggle based on the lower order bits. A2 is set to toggle with A3 is HI (meaning it will go HI to LO on the next clock) and A1 is set to toggle when both A2 and A3 are HI (meaning they will both goes from HI to LO on the next clock).

 

Anhnha, your clock is correct, but the interconnects among the flip flops are a mess.
Think about how A2 needs to know the state of A1 to do its job right. See if that helps.

Why does A2 need to know the sate of A1?

Look at the circuit and see which FF is the lsb and which FF is the msb. Of course, it sure would have been nice for Anhnha to label his schematic so that other people aren't having to guess what was meant -- something that they really should have learned by now given how many times it has been pointed out to them.

Oh, and don't ground those unused inputs, that would be bad. Think pull-ups.

So you would put a pull-up on the unused pins of an XOR or on the PRE/CLR inputs of a FF?

 

Just connecting unused pins to ground may not do what you want. What happens with an AND gate when any pin is connected to ground?

What are the pins on the side of the logic gates for?

Actually before doing this, I read the article below.
http://www.electronicspoint.com/resources/going-digital.19/
However, I noticed that there is no difference where these pins are connected to ground or not.
Here is what the article says:

What method did you use to design this? Why isn't the output of A1 connected to any other flip-flop but A1?

I tried the one with 5 flip flops but I didn't work. So I just copied the simple one in the site given above to test.
http://www.zeepedia.com/read.php?d_flip-flop_based_implementation_digital_logic_design&b=9&c=32

Of course, it sure would have been nice for Anhnha to label his schematic so that other people aren't having to guess what was meant -- something that they really should have learned by now given how many times it has been pointed out to them.

I thought it is clear enough.
Q3 is the lsb and Q1 is the msb.

 

Note that the instructions provides clearly state that unused I/O must be connected to pin 8 and that pin 8 must be connected to the common ground of the circuit. Though this doesn't make any physical sense given that grounding any input on an AND gate should for the output LO regardless of any of the other inputs.

Regardless of what the simulator does or doesn't allow you to get away with, get in the habit of designing your circuits properly so that the same schematic you simulate will work correctly in the real world.

And "thinking something is clear enough" is a pretty common way to regularly ensure that things get garbled in communication. Don't force people -- particularly people that you are asking for free help from -- to reverse engineer your circuits to figure out what you are doing. Have the courtesy to properly comment your schematics.

 

I tried the one with 5 flip flops but I didn't work. So I just copied the simple one in the site given above to test.
http://www.zeepedia.com/read.php?d_flip-flop_based_implementation_digital_logic_design&b=9&c=32.

I think you have it right (except for unconnected inputs) I am not used to seeing the schematic drawn MSB-LSB, and was confused.

 

Why does A2 need to know the sate of A1?

Look at the circuit and see which FF is the lsb and which FF is the msb. Of course, it sure would have been nice for Anhnha to label his schematic so that other people aren't having to guess what was meant -- something that they really should have learned by now given how many times it has been pointed out to them.



So you would put a pull-up on the unused pins of an XOR or on the PRE/CLR inputs of a FF?

I should have looked at the circuit a bit longer, because I did, in fact, reverse the flip flops. Thanks for pointing out that the LSB is on the right. Things look much better now!

No, my reference to pull-ups was just for the unused pins on the flip flops, the preset and clear lines.

 

So how does a FF behave if you put pullups on the PRE and CLR inputs? Note that (at least as indicated by the symbol) these two inputs are active-HI.

 

Well, I got the result now. I realize that I missed one important information from the guideline:

 

Note that the instructions provides clearly state that unused I/O must be connected to pin 8 and that pin 8 must be connected to the common ground of the circuit. Though this doesn't make any physical sense given that grounding any input on an AND gate should for the output LO regardless of any of the other inputs.

Regardless of what the simulator does or doesn't allow you to get away with, get in the habit of designing your circuits properly so that the same schematic you simulate will work correctly in the real world.

And "thinking something is clear enough" is a pretty common way to regularly ensure that things get garbled in communication. Don't force people -- particularly people that you are asking for free help from -- to reverse engineer your circuits to figure out what you are doing. Have the courtesy to properly comment your schematics.

I tried to include all necessary info just missed that one.

 

So how does a FF behave if you put pullups on the PRE and CLR inputs? Note that (at least as indicated by the symbol) these two inputs are active-HI.

Aaaaak! I saw the little circles and thought that meant active low inputs. Best if I get out this thread.

 

From someone trying to make sense of SPICE ...
Okay unused inputs and outputs are connected to "Pin 8" and Spice realizes these are simply not used. The 5-input Exclusive-OR/NOR can be many different gates????
How does this simulate operation with real gates?
0 to 1 V logic levels???? What logic family is this?