wow! complicated! dunno what a four-state asynchronous machine is, sorry.The circuit requires a four-state asynchronous machine. You can find lots of state diagrams on the web, though I haven't looked at any of them in detail. Lots of stuff on the web is wrong (Gasp! ) - as we saw earlier.
Every change of level of either input must generate a clock for the state machine, however because that clock looks at the levels of the quad' inputs, it is typically necessary to delay the clock slightly to meet the setup time requirement for the state machine flip flops. If the the quad' signals are not clean with adequate slew rate, they must be cleaned up.
[EDIT - Sorry, I conflated a machine that produces separate UP and DOWN clocks with one which produces one clock and a direction signal - but the basic notion of what must happen in terms gen'ing the clock & dir are the same.
Where many attempts go wrong is in dealing properly with a reversal that changes the level of only one of the inputs. If the encoder is rotating CW, changes the level of (say) the A output, an UP output clock must be generated (assuming CW is UP) after setting (or not changing) the DIRECTION signal. If the direction of rotation is then changed so that A goes back to its earlier level, the state of the DIRECTION output must change and a DOWN output clock be generated - which is all covered in the state diagram. This can all happen in a small fraction of a degree of rotation, even for an ultra-low resolution encoder. I know of a case where decoding was done in firmware and was in use for years before anyone realized the code was wrong. Fortunately it was on a machine where rotation was continuous in one direction when the encoder output was necessary.
but i think..hard.. that i get your drift. Not sure how cluey the Stepperature board is. Gunna test it to the max.