schematic for 8 bit programmable frequency divider

Thread Starter

V3eni

Joined Jan 23, 2020
2
8 bit programmable frequency divider with upward counting and comparator circuit.
Only hct/hc ic allowed. The oscilator should provide two clock signals with the freq (1) 5.7HZ
and (2) 540 kHZ and also a bistable mode (to manual control the clock signal)
I only designed the block diagram, I need your help now to design the schematic!!!
 

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WBahn

Joined Mar 31, 2012
26,266
8 bit programmable frequency divider with upward counting and comparator circuit.
Only hct/hc ic allowed. The oscilator should provide two clock signals with the freq (1) 5.7HZ
and (2) 540 kHZ and also a bistable mode (to manual control the clock signal)
I only designed the block diagram, I need your help now to design the schematic!!!
How does your block diagram provide for the bistable mode?

If you have an adequate block diagram, then the translation from that to a schematic should be reasonably straightforward, or should at least make it fairly obvious which specific issues need to be addressed.
 

Thread Starter

V3eni

Joined Jan 23, 2020
2
So this is what i've done so far... the clock generator is not important for now, i'll design it later using 555. My question now... (this project should later be done on a PCB and i have concerns about the selecting value for dividing. I was thinking to use a 8 dip switch but the switch should provide either 0 or 1 logic not 1 or off (grey square in proteus) how can i do that?Screenshot (7).png
 
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