Hello,In the circuit below which LTSPICE file are attached. We have a Q1 transistor.
I was told about several methods to see if the PNP is under saturation
1.The Ic/Ib ratio which is HFE, but in the data sheet i det see what exact values are considered to be saturation and in what HFE it will be linear?
2.Vce plot shown below, again i am not sure what Vce says its saturated and what its linear because in the datasheet there are two cases2
3.delay between the base and the collector voltages.How can i see In the datasheet the delay which will telll me that the delay is linear and when the delay says that my PNP is saturated?
Thanks.
https://www.mouser.com/datasheet/2/115/DIOD_S_A0011167377_1-2513105.pdf

 

hi yef,
Look at this image for the Vce sat, which is a function of the Ic.

Also this link for HFE Hfe
https://www.electronics-notes.com/a...mponents/transistor/current-gain-hfe-beta.php

E

 

A PNP is in saturation when both the collector voltage and the emitter voltage are higher (more positive) than the base voltage.

 

Hello Ericgibs,what practical way In ltspice you reccomend me to see if my PNP is saturated or not ?
Thanks .

 

hi yef.
This plot shows the Q1 Vce at the pulse peak.

Do you think it is saturated??
E

 

I was told about several methods to see if the PNP is under saturation

I think a more definitive method is to monitor the collector-base voltage. When that junction becomes forward biased, the transistor is operating in saturation mode.

I did saturation tests on BC337 and 4-5 other transistors. The data showed that transistors will saturate at lower Ic/Ib ratios than specified in the datasheets.

Data is in this thread.

 

Hello,V_cb junction is forward biased,another problem is my Vbe is -0.9V-1V.
Large Vbe make very large Ic given the datasheet how can i know what is the Ic when the PNP in linear state?
Thanks.
https://www.diodes.com/assets/Datasheets/MMDT3906.pdf

 

This part of the data sheet was found by having a current source on the collector. (no resistors)
The base is also driven by a current source. No resistors.
There is no comment about "saturation". The voltage from E to C is -1V.

 

Hello,In the circuit below which LTSPICE file are attached. We have a Q1 transistor.
I was told about several methods to see if the PNP is under saturation
1.The Ic/Ib ratio which is HFE, but in the data sheet i det see what exact values are considered to be saturation and in what HFE it will be linear?
2.Vce plot shown below, again i am not sure what Vce says its saturated and what its linear because in the datasheet there are two cases2
3.delay between the base and the collector voltages.How can i see In the datasheet the delay which will telll me that the delay is linear and when the delay says that my PNP is saturated?

The first thing that you have to do is define what, for your purposes, "saturation" means.

A common definition is that the boundary between the active and the saturation regions is when the collector-base junction is 0 V (i.e., at the boundary between it being reverse-biased to and forward-biased).

While this has the convenience of being a well-defined criterion, and is therefore very attractive to the ivory-tower academia crowd that write textbooks, from a practical standpoint it is pretty much useless. This is evidenced by the fact that no data sheet (that I am aware of) makes mention or use of it at all, and since data sheets strive to provide information that is of use to people trying to use the device in practical circuits....

The reality is that the transition from active to saturation, from any practical perspective, is ill-defined. It is smooth and it occurs over a range of operating points. Virtually no circuit is going to experience a significant change in behavior going from Vbc being reverse-biased by 100 mV and being forward-biased by 100 mV. If your goal is to operate the circuit in the active region, you are almost always going to strive to stay well away from it on one side because the active-region performance is changing too much well before you reach it, and if your goal is to operate the circuit in the saturation region, you are almost always going to strive to stay well away from it on the other side because power dissipation and/or Vce voltage drop is too much until you are well beyond it. If you think that you can design a circuit based on some hard and specific demarcation between active and saturation, you are probably about to go down a rabbit hole on a fool's errand.

So you need to ask yourself why you are even trying to answer the question about whether it is in saturation or not, and then decide on a criterion that makes sense given that reason.

Manufacturers of small-signal diodes generally specify saturation performance at an HFE of 10. That is NOT because they are defining that to be the boundary between active and saturation. It is because they want to provide information that is relevant to people designing practical circuits that want to operate the device in saturation. The value of 10 was arbitrary and can likely be traced to the early days of transistors becoming commercially-viable products. One of the early manufacturers chose 10 for reasons that are almost certainly lost to history and other manufacturers used the same value so that potential customers could easily compare their new/better device's performance to the competition. It quickly became a defacto standard (in a soft way).

 

I learned how to define transistor modes (regions) of operation from Tocci:

You can borrow the book here.

 

Hello,I have attached two LTSPICE files.There are two kinds of plots,saturated and non saturated shown below.
I dont understand where is the significant delay in the signal in the saturated state.
How can i see that there is stretch in the non saturated PNP?
Saturated PNP
non saturated PNP

 

See

 

do you see the logic in the plots?
I dont see by the plot when its saturated or not

 

do you see the logic in the plots?
I dont see by the plot when its saturated or not

V(c) is the dynamic output impedance of the transistor. I change (increase) the collector current at a fixed base current. When V(c) begins to increase smoothly, a transition from the saturation mode to the amplification mode occurs. Note - a smooth transition. There is no clear boundary between the transistor modes.

 

Alternative approach. You can do all this in LTspice too. But I like to use Qspice as it is more convenient program.

 

Hello , How can you see in your ouput plots where is saturation and where is linear?
How can you see by the output impedance the state of the PNP?

 

When the output differential resistance is small, this is the saturation mode. If this resistance is high, this is the amplification mode. There is no clear boundary. Moreover, the resistance depends on both the base current and the collector current. You can also define the amplification mode when the forward current of the base-collector junction is small - microamperes or less, but it is difficult to determine. This is due to the indefinite value of the Beta transistor. The voltage at the PN junction cannot be taken as a criterion due to the voltage drop on Rb, which in turn is nonlinear.