PWM duty cycle detector

KMoffett

Joined Dec 19, 2007
2,918
Digital is not my forte. But, it seems like there would be a mostly digital method. Trigger a monostable at the start of the PWM pulse, with a period equal to 10% of the PWM . Compare the fall of that with the fall of the PWM pulse. If the PWM pulse falls first then alarm. If the monostable falls first, then no alarm. Can't get my head around the digital logic for that. Maybe I need more coffee...or less. ;)

Ken
 

MikeML

Joined Oct 2, 2009
5,444
I already gave you a single pole. Adding an opamp does nothing to that. Why do you think you need a filter with a sharper roll-off?
 

Thread Starter

Martino Chiro

Joined May 1, 2015
128
I already gave you a single pole. Adding an opamp does nothing to that. Why do you think you need a filter with a sharper roll-off?
I
I already gave you a single pole. Adding an opamp does nothing to that. Why do you think you need a filter with a sharper roll-off?
I suppose i can get a fast response. If an active 1 pole filter is faster (then a 1 pole RC), i suppose an active 2 pole filter is better.
 

MikeML

Joined Oct 2, 2009
5,444
An active 1Pole is exactly equivalent to a RC wrt freq response and rise time. The only thing that the opamp does is provide buffering.

A two-pole active can have a sharper roll-off and/or faster settling.
 

Thread Starter

Martino Chiro

Joined May 1, 2015
128
An active 1Pole is exactly equivalent to a RC wrt freq response and rise time. The only thing that the opamp does is provide buffering.

A two-pole active can have a sharper roll-off and/or faster settling.
Maybe i have misunderstood your previous post n. 19:
"The only advantage an active filter over the single pole RC filter I used is that the LED would turn on more abruptly, and follow changes in duty cycle a bit faster."
Do you refer to a 1 or 2 poles active filter ? Or doesn't matter the number of poles, just matter if it is an active filter ?
 

Thread Starter

Martino Chiro

Joined May 1, 2015
128
Digital is not my forte. But, it seems like there would be a mostly digital method. Trigger a monostable at the start of the PWM pulse, with a period equal to 10% of the PWM . Compare the fall of that with the fall of the PWM pulse. If the PWM pulse falls first then alarm. If the monostable falls first, then no alarm. Can't get my head around the digital logic for that. Maybe I need more coffee...or less. ;)

Ken
Thank You Ken,
another good idea to detect a PWM value.
 

AnalogKid

Joined Aug 1, 2013
11,048
Digital is not my forte. But, it seems like there would be a mostly digital method. Trigger a monostable at the start of the PWM pulse, with a period equal to 10% of the PWM . Compare the fall of that with the fall of the PWM pulse. If the PWM pulse falls first then alarm. If the monostable falls first, then no alarm. Can't get my head around the digital logic for that. Maybe I need more coffee...or less. ;)
Ken
One monostable plus one flipflop. The input signal goes to the data input pin of the ff, and it also triggers the monostable. The output of the monostable clocks the ff with its trailing edge. The ff Q output is the over/under 10% state of the input signal. High means the input duty cycle >10%.

ak
 

Thread Starter

Martino Chiro

Joined May 1, 2015
128
One monostable plus one flipflop. The input signal goes to the data input pin of the ff, and it also triggers the monostable. The output of the monostable clocks the ff with its trailing edge. The ff Q output is the over/under 10% state of the input signal. High means the input duty cycle >10%.

ak
Very interesting solutiom AnalogKid,
i have a question: how can be minimized (or avoided) any risk of metastability on the flip flop when the duty cycle is 10% and data and clock will switch at the same time ?
 

Thread Starter

Martino Chiro

Joined May 1, 2015
128
Since an opamp is not required to create a single-pole filter, "active filter" refers to two or more poles...
My understanding of the RC low pass filter, is that, with a 10K and 3.3uF values, there are 150-200msec to get the 0,528V.
If i use an active (2 poles) filter, can i get the 0,528V faster ?
 

AnalogKid

Joined Aug 1, 2013
11,048
Very interesting solutiom AnalogKid,
i have a question: how can be minimized (or avoided) any risk of metastability on the flip flop when the duty cycle is 10% and data and clock will switch at the same time ?
The setup time for a flipflop is around 5 to 20 nanoseconds depending on the type and process. That's a very small window for error, but if the input and clock edges are that close together, or if the PWM edge has some phase noise, then the output of the flipflop is going to jump around. Worst case, it will hop back and forth between the less than and greater than states every other cycle, effectively dividing the PWM frequency by two.

With some feedback from the output of the flipflop to the monostable you can time-domain hysteresis, changing the monostable's pulse width for the next input edge depending on the current ff state. This is the same as adding hysteresis to an analog comparator to prevent noise bursts on the output, with the same benefits and consequences..

ak
 

KMoffett

Joined Dec 19, 2007
2,918
Martino,

You didn't spec a tolerance window for indicating a period below 10%. How stable is the PWM pulse period? Is it part of a feedback loop? I don't remember you saying what you will do if the pulse width is at or below 10%. Is a "flickering'" output good enough to know that you are "at" the limit.

Ken
 

MikeML

Joined Oct 2, 2009
5,444
My understanding of the RC low pass filter, is that, with a 10K and 3.3uF values, there are 150-200msec to get the 0,528V.
If i use an active (2 poles) filter, can i get the 0,528V faster ?
A lot faster. Here is a comparison of the settling time of a 4Hz one-pole RC and a 100Hz 2-pole Butterworth low-pass filtering a 10% duty-cycle 5kHz pwm. This is effectively the step response from 0% pwm to 10% pwm.

Note the settling time, and the carrier feed through after settling. Bit of overshoot, though.

55.gif 55r.gif
 

Thread Starter

Martino Chiro

Joined May 1, 2015
128
A lot faster. Here is a comparison of the settling time of a 4Hz one-pole RC and a 100Hz 2-pole Butterworth low-pass filtering a 10% duty-cycle 5kHz pwm. This is effectively the step response from 0% pwm to 10% pwm.

Note the settling time, and the carrier feed through after settling. Bit of overshoot, though.

View attachment 85058 View attachment 85059
Impressive. Why a 100Hz filter now, from a 4Hz ?
 

MikeML

Joined Oct 2, 2009
5,444
Impressive. Why a 100Hz filter now, from a 4Hz ?
Because in the final analysis, the only thing that matters is carrier feed-through after the filter settles. I found empirically that a 100Hz 2 pole has ~ the same ripple (a bit less) than the 4Hz brute force one...
 

Thread Starter

Martino Chiro

Joined May 1, 2015
128
Because in the final analysis, the only thing that matters is carrier feed-through after the filter settles. I found empirically that a 100Hz 2 pole has ~ the same ripple (a bit less) than the 4Hz brute force one...
That means that i can use the same 100Hz 2 poles filter, also if the PWM is working at 1KHz ?
 

Thread Starter

Martino Chiro

Joined May 1, 2015
128
Good place to start. The answer depends on how much ripple the following circuit(s) can tolerate.
The 20Hz filter i try to design is here. From the datasheet of the LT1018 (the other half) is not clear what is the parameter that let the designer choice the max. ripple. I used 1db.
The parameters of the filter are:
Passband attenuation: 3dB (is ok ?)
Stopband attenuation: 30dB (is ok ?)
Passband Frequency: 20Hz
Stopband Frequency: 400Hz (is ok ?)
Gain: 1
But is not so fast as your.
Moreover, is the LT1018 suitable to be used for this 20Hz filter ?

upload_2015-5-3_22-56-33.png
 
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