Hello,I’m designing a 555 timer circuit in astable mode to get ~50% duty cycle. I used two diodes to separate the charging and discharging paths, and used 100kΩ resistors on both paths (R2 = R1 = 100k). My reasoning was that since T_high = T_low, this should give ~50% duty cycle and when I tested it on the oscilloscope, it showed 49.5% / 50.5%, which was what I wanted.

My prof today looked at my design and said that I should have used a 101kΩ resistor in the Vcc side instead of the 1kΩ I used because resistors should be equal and its not right to use 1k for 50% duty cycle. I’m not sure why this matters in this design, since I thought with the diodes separating the paths, the timing should just depend on RA and RB now not the resistor connected to Vcc.

Also, My reasoning and calculation to justify my duty cycle is that
R1=charging path resistor
R2 = discharging path resistor
duty cylce =t_high/T_total = R1/(R1+R2)=100/(100+100)=50%

am I wrong for not considering R=1k at all in this formula ? my assumption was that R=1k it is just helping the capacitor charge fully, but it is not in the timing formula. and why should I use 101k for R ?


Would really appreciate if someone can clarify this.Thanks in advance

 

am I wrong for not considering R=1k at all in this formula ?

Yes. It is in the charging path but is not in the discharge path. Do you understand how the 555 operates?
Btw, you should use consistent component designators. Your text mentions RA and RB but your schematic shows R1 and R2. The 1k resistor has no designator.

 

Yes. It is in the charging path but is not in the discharge path. Do you understand how the 555 operates?
Btw, you should use consistent component designators. Your text mentions RA and RB but your schematic shows R1 and R2. The 1k resistor has no designator.

What I had in mind based on my understanding ws the diodes separate the capacitor’s charge and discharge paths. When the output is HIGH,pin 7 is disconnected the capacitor charges through R1=100k and R=1k(yes i obviously Wrong for not including R=1k in the charging path)and when the output is LOW, pin 7 is grounded and it discharges through R2 =100k. Based on this I’m thinking duty cylce will be (R+R1)/(R+R1+R2) and with my current resistors values I will get 101/201 almost 50% duty cycle.
could you pls tell me if my reasoning is right?
And now that I’m thinking What my prof meant was that to use 101k for R2 (discharging resistor ) so that it will be equal to R+R1=101k to get exactly 50% duty cycle, not almost 50%. And that makes sense.
Thanks!

 

could you pls tell me if my reasoning is right?

It is now.

 

other than understanding circuit operation, splitting hairs over 100k vs 101k makes little sense.
did you professor define to what accuracy this 50% duty cycle is supposed to go? and what is the tolerance of parts your lab uses?
in practice, this is hardly noticeable. good way to get 50% duty is to use flip-flop to divide input frequency by 2. much cheaper than using parts with very tight tolerances.

 

other than understanding circuit operation, splitting hairs over 100k vs 101k makes little sense.
did you professor define to what accuracy this 50% duty cycle is supposed to go? and what is the tolerance of parts your lab uses?
in practice, this is hardly noticeable. good way to get 50% duty is to use flip-flop to divide input frequency by 2. much cheaper than using parts with very tight tolerances.

we don’t have strict tolerance requirements, and on the oscilloscope I was already getting ~49.5–50.5%, which is fine. I think my professor’s point wasn’t really about 100k vs 101k accuracy, but more about the fact that since I chose to separate the charge and discharge paths using diodes, I should match both paths properly ,otherwise, I could’ve just used the basic circuit and gotten similar results without adding diodes. Also, for this project we aren’t allowed to use flip-flops only diodes and resistors. I’m open to any suggestions though, my duty cycle looks good, but I noticed the output voltage of my astable stage is lower than expected (Vcc is 8V but the output is around 3V instead of 4V), even though I’m using precise resistors so I’m trying to understand where this drop is coming from and whether there’s a better way design a circuit for 50% duty cycle

 

I don't know why you are using two diodes to get a duty cycle D ≈ 50%. They are not neccesary.

You know that:
$$D = \frac{t_c}{T} \quad (1)$$

or

$$t_c = DT \quad (2)$$

Also, remember that:

$$T = t_c + t_d \quad (3)$$

Replacing (2) in (3) we get:

$$ T = DT + t_d \quad (4)$$

if we isolate \(t_d\) from (4) then:

$$t_d = T(1-D) \quad (5)$$

Now, remember that:

$$t_c = (R_A + R_B)\cdot C \cdot \ln(2) \quad (6)$$

and

$$ t_d = R_B \cdot C \cdot \ln(2) \quad (7) $$


To find the value of \(R_B\), we isolate this value from eq. (7)

$$ R_B = \frac{t_d}{C \cdot \ln(2)} \quad (8)$$

To find \(R_A\) we isolate \(R_A\) from (6):

$$ R_A = \frac{t_c}{C \cdot \ln(2)} - R_B \quad (9) $$

In order to design an astable circuit with a specific output frequency, you must take into account the duty cycle and the key point is to propose a value for the capacitor, for example, assuming you want to desing a system with:

D = 50.1% = 0.501
f = 1kHz
assuming a capacitor C = 1nF, then:

$$ T = \frac{1}{f} = 1 ms \\ $$
Charging time would be
$$ t_c = DT = (0.501)(1 \times 10^{-3}) = 501 \, \mu s$$

Use eq. (5) to find the discharging time

$$ t_d = T(1-D) = (1 \times 10^{-3})(1 - 0.501) = 499 \, \mu s $$

Now use eq. (8) to find \(R_B\)

$$ R_B = \frac{t_d}{C \cdot \ln(2)} = \frac{499 \times 10^{-6}}{(1 \times 10^{-9})(\ln(2))} = 719.9 k\Omega $$

Finally, the value of \(R_A\) is:
$$ R_A = \frac{t_c}{C \cdot \ln(2)} - R_B = \frac{501 \times 10^{-6}}{(1 \times 10^{-9})(\ln(2))} - 719.9 \times 10^{3} = 2.89 k\Omega$$

I implemented this circuit using 1% resistors and got the following output signal

 

Why are you making it complicated? If you want exactly 50% duty cycle, you don't need any diodes, nor a resistor to V+. One resistor between pins 3 and the junction of pins 2 and 6 does it.

 

hi Phy,
As per post #8.
E

 

An afterthought. . .
A CMOS timer with that circuit will give a more accurate 50% duty cycle because the output dropout voltage (the voltage between the rail and the output voltage) is the same for both logic 1 and logic 0 outputs, on the old bipolar device (does anyone really still use them?) the logic 0 gets closer to Vss than the logic 1 gets to Vcc so the waveform won't be EXACTLY square. Capacitor charge time will take fractionally longer than capacitor discharge time.
But if anyone wanted PRECISELY 50% they would follow the oscillator with a divide by 2 (as in CD4047)

 

Hello,I’m designing a 555 timer circuit in astable mode to get ~50% duty cycle. I used two diodes to separate the charging and discharging paths, and used 100kΩ resistors on both paths (R2 = R1 = 100k). My reasoning was that since T_high = T_low, this should give ~50% duty cycle and when I tested it on the oscilloscope, it showed 49.5% / 50.5%, which was what I wanted.

My prof today looked at my design and said that I should have used a 101kΩ resistor in the Vcc side instead of the 1kΩ I used because resistors should be equal and its not right to use 1k for 50% duty cycle. I’m not sure why this matters in this design, since I thought with the diodes separating the paths, the timing should just depend on RA and RB now not the resistor connected to Vcc.

Also, My reasoning and calculation to justify my duty cycle is that
R1=charging path resistor
R2 = discharging path resistor
duty cylce =t_high/T_total = R1/(R1+R2)=100/(100+100)=50%

am I wrong for not considering R=1k at all in this formula ? my assumption was that R=1k it is just helping the capacitor charge fully, but it is not in the timing formula. and why should I use 101k for R ?


Would really appreciate if someone can clarify this.Thanks in advance
View attachment 350901

Hi,

If you really have to do it this way and you are worried about the effect of the 1k, then just add another 1k in series with D2. That gives you 101k in the charge path and 101k in the discharge path.

Since there are other differences we have not addressed yet, it would be typical to put a potentiometer connected to both R1 and R2 and the arm to C2. That allows adjusting for a 50 percent duty cycle to some given tolerance.

The other solution already given is to use the output rather than the discharge pin to charge and discharge C2. That only requires one resistor. That should give close to a 50 percent duty cycle also. One caveat would be that the output low state may not go all the way to zero, which could cause the duty cycle to be something different than 50 percent. To compensate you could probably bias the control voltage pin with a resistor to +Vcc.

The other solution given was to use a divide by 2 flip flop. That means you can have just about any duty cycle out of the 555 and still get a nearly perfect 50 percent duty cycle out of the flip flop. As long as the duty cycle does not vary, the output should stay at a 50 percent duty cycle.

To analyze these circuits in detail you can look up the internal functional diagram. It uses comparators and resistors and a flip flop so it's not too difficult to analyze just about any connection we'd like to try.