Hi everyone.
I am trying to generate a square wave signal with 50% duty cycle with the help of circuit given in https://www.electronics-tutorials.ws/waveforms/555_oscillator.html (the circuit with heading '50% Duty Cycle Astable Oscillator'). I am using C = 0.01uF and R = 10kohm (5% tolerance). According to the calculations, the generated frequency should be 7215 Hz but the frequency observed at the oscilloscope is 5.81kHz when power supplied to the timer is 8V. Can anyone tell why is this so? If anyone has an idea of a better timer circuit which can generate perfect square wave for longer duration of time, please suggest. I am using STMicroelectronics CHN NE555N KJW949 timer for it.

 

There are multiple oscillators in that article. It would be better if you posted the schematic for your circuit.

 

There are multiple oscillators in that article. It would be better if you posted the schematic for your circuit.

R2 = 10kohm C = 0.01uF

 

What type of capacitor are you using and what is its tolerance?

 

What type of capacitor are you using and what is its tolerance?

I am using a 103 AEC ceramic capacitor but how to find its tolerance?

 

I am using a 103 AEC ceramic capacitor but how to find its tolerance?

You might find it in the manufacturer datasheet. If the manufacturer has several tolerances and dielectrics, you're out of luck because SMT caps have no markings.

Ceramic caps can have tolerances of:
Z5U +/-20%, -20/+80%
X7R +/-5%, +/-10%, +/-20%
NP0 can be as low as +/-1%

NP0 is also temperature stable.

BTW, your timing resistor could account for as much as 10% of the error you're seeing.

 

Two points to note.

1) Because of tolerances in component values and variations with temperatures, etc. you cannot expect to achieve exact results with fixed values. Use a variable resistor to trim the frequency.

2) If you need exactly 50% duty cycle, generate twice the frequency and feed this into a divide-by-2 circuit, i.e. a T-type flip-flop.

 

I have developed a way to get 50% duty cycle off of a 555 hysteric oscillator. First you have to understand why it is not 50%, the linked article explains this. The lower the voltage the worse the problem gets. Here is a fix for it we're like 5 volts.

Rail to Rail 555 Output

 

If R1 was removed, that circuit should give a 50% duty cycle; aside from the first cycle when the cap is charging from ground.

The explanation for why R1 is necessary is erroneous. The capacitor only charges to 0.67Vcc. R1 is unnecessary and affects the duty cycle.

 

If R1 was removed, that circuit should give a 50% duty cycle; aside from the first cycle when the cap is charging from ground.

The explanation for why R1 is necessary is erroneous. The capacitor only charges to 0.67Vcc. R1 is unnecessary and affects the duty cycle.
View attachment 325928

True, if it were a CMOS 555, but the output of a bipolar 555 gets closer to the negative rail than the positive, so needs the charging resistor to be lower than the discharging resistor. You're right - it's a poor explanation.
I gave up bipolar 555s long ago!

If you want 50% duty cycle, use a 4047. It has a divide by two stage built in.

 

True, if it were a CMOS 555, but the output of a bipolar 555 gets closer to the negative rail than the positive, so needs the charging resistor to be lower than the discharging resistor. You're right - it's a poor explanation.
I gave up bipolar 555s long ago!

Aside from the first pulse, the capacitor voltage stays between 0.33Vcc and 0.67Vcc. How close the output gets to the rails doesn't matter.

 

Updated schematic

 

Aside for the first pulse, the capacitor voltage stays between 0.33Vcc and 0.67Vcc. How close the output gets to the rails doesn't matter.

Vol seems to be about 0.1V and Voh seems to be about 1.4V less than Vcc.
Assume a 10V supply. Thresholds are 3.33V and 6.67V. Output voltages are 0.1V and 8.6V.
Starting after the second pulse: The capacitor is at 3.33V, and it has to charge to 6.67V from a source of 8.6V, that is 3.33V/5.27V. So the time constant is -RClog(1-3.33/5.27) = 0.999RC
The discharge is from 6.67V to 3.33V from a 0.1V source, is -RClog(3.23/6.57) = 0.719RC

 

Vol seems to be about 0.1V and Voh seems to be about 1.4V less than Vcc.
Assume a 10V supply. Thresholds are 3.33V and 6.67V. Output voltages are 0.1V and 8.6V.
Starting after the second pulse: The capacitor is at 3.33V, and it has to charge to 6.67V from a source of 8.6V, that is 3.33V/5.27V. So the time constant is -RClog(1-3.33/5.27) = 0.999RC
The discharge is from 6.67V to 3.33V from a 0.1V source, is -RClog(3.23/6.57) = 0.719RC

OK, it matters. Makes me wonder why so many people think that configuration gave a 50% DC?

 

If you want stability and accuracy, use a quartz crystal on a n-stage divider IC.

 

OK, it matters. Makes me wonder why so many people think that configuration gave a 50% DC?

It does give 50% on a CMOS version, because the MOSFET output stage looks like a resistor to the supply. The two resistances are not equal, but they are small compared to the timing resistor.

I note that the title of this thread refers to a LMC555 (CMOS version) but the text in post #1 refers to a NE555 (Bipolar version)

 

If you want an exact 50% duty-cycle, independent of any component tolerances or voltage levels, then set the 555 astable for twice the frequency you want (duty-cycle is not important) and run the signal through a divide-by-2 toggle flip-flop.

 

If you want an exact 50% duty-cycle, independent of any component tolerances or voltage levels, then set the 555 astable for twice the frequency you want (duty-cycle is not important) and run the signal through a divide-by-2 toggle flip-flop.

CD4047 and CD4060 will do that in one IC. CD4047 will be rather more accurate on frequency.

 

The Nat Semi LMC555 datasheet doesn't specify a symmetrical output voltage swing.

 

The Nat Semi LMC555 datasheet doesn't specify a symmetrical output voltage swing.

Data on the output stage is a bit scarce in that data sheet! But I think you can infer from "CMOS" that the output stage consists of two complementary MOSFETs in common source configuration. Each will have a different Rds(on) especially as it seems that the low output is far more capable than the high, but if all it is driving is the timing resistor then the ratio of Ton to Toff will be (Rtiming+Rds(on)Pch)/(Rtiming+Rds(on)Nch) which will tend to unity as Rtiming increases.
I wouldn't expect it to maintain accuracy if it was driving a load in addition to the timing resistor.