And doesn't the circuit diagram in message #8 do exactly that?View attachment 179703
That's how it should look like
And doesn't the circuit diagram in message #8 do exactly that?View attachment 179703
That's how it should look like
Whatever it says on the datasheet of the part you decide to use.what would be the threshold values of the schmitt trigger if i have a logic input from 0 to 3.3v?
HiHere is a grab from the innergoogle, from some old National Semiconductor publication. For your application, reverse D1 and place the R in parallel with the C. The first inverter also can be a 14 rather than an 04. The requirements for the gates is that they both be inverterrs, and that the second one must be a Schnitt Trigger type. Other than that, they can be any TTL or CMOS variety that matches the rest of your circuits.
A possible issue is that for some logic families, the pull up current capability is much less than the pull down. This means the first gate will have a harder time charging up the capacitor than in the original circuit where it is discharging the capacitor current down to GND. One solution is to use one of the newer, more "stiff" CMOS varieties like the AC or ACT series.
After ***six*** posts, we still have *zero* timing information from you, so we cannot recommend component values.
ak
HiI don't know what you mean by "account for". In my circuit, the incoming high-to-low moves quickly to the output, slowed only by two gate delays and the time it takes for the first gate to charge up the timing capacitor. Depending on the circuit timing requirements - ***which we still do not know*** - this might be a trivial error. The mvas circuit is better about this, with only a 1-gate propagation delay.
ak
The Low R value is specifically there to prevent "Sink Current" from being an issue with the capacitor discharge.Depending on the ratio of the minimum input pulse width and the maximum additional time he wants added, there could be a problem with either the Low R value or the current sink capability of whatever is driving this circuit. Still, the second AND input does solve the turn on edge delay problem.
ak
what are the 2 inputs of the schmidt trigger?A single gate delay on the initial falling edge
Adds the RC "time delay" only after the rising edge of the pulse
HIGH R + C = Time Delay
Low R + Diode discharges cap very quickly - ie while the Pulse is still low.
Stretches only the "0" pulse
View attachment 179720
?what are the 2 inputs of the schmidt trigger?
Awhat are the 2 inputs of the schmidt trigger?
Are you designing a circuit using IC's or are you designing an IC ?i want to design a circuit for stretching the "0" output of my signal. I have seen the Monostable multivibrator but it stretches the "1" output. is there anyway flipping it or another topology for realizing that?
Designing an IC so i don't have this ready schmitt AND and i will have to design it by myselfAre you designing a circuit using IC's or are you designing an IC ?
Like with a counter that has a high speed clock, that starts counting down on the rising edge ?is there a way to stretch it digitally without using the RC circuit for 100ns only?