A very simple idea ...i just have a digital output of a D-flipflop and i want to stretch the "0" not the "1"
It seems that there's misunderstanding as the clock is not the output i want to stretch. The output is the D-flipflop output or let's say a digitals out with different pulse lengths. The length of "1" shouldn't be affected and the desired output depends only on the output of the D-flipflopSo...
How much longer?
- What’s the frequency of the clock?
- What’s the desired output length?
- What happens to the length of the “1” output!
- If the D output goes high then low while your desired output is “0” then what happens?
thanks for your answer but i'm designing this IC so no ready to use ICsThis is overkill, but requires no code, even though it is an ARM UP inside
and a bunch of other stuff.
Can stretch a pulse from uS to years if you want, and anything in between.
View attachment 179561
As you can see in right hand columns lots of other resources on chip as well.
The problem that the pulse length is varying and i want this time constant to be added to the original pulse widthA very simple idea ...
View attachment 179610
It works with very short input pulses.
The are also High Speed "Falling Edge" Monostsable Multivibrator IC's
an example IC with a "Falling Edge" input ...
Please cut the useless space of the circuit before you upload to the forum, the circuit already cut the space.
It seems that there's misunderstanding as the clock is not the output i want to stretch. The output is the D-flipflop output or let's say a digitals out with different pulse lengths.
There’s the misunderstanding. I didn’t get that the input pulse length varied. The point of my comment is what would happen if you received two pulses during the period of your lengthened pulse? (excuse the rough graphic)The problem that the pulse length is varying and ...
that wouldn't be a problem, i don't have to detect it as long as it's in the LOW pulse
i think that would still have the problem when having longer input pulses. additionally it will be triggered with the raising edge of the input which is another problemHere is a grab from the innergoogle, from some old National Semiconductor publication. For your application, reverse D1 and place the R in parallel with the C. The first inverter also can be a 14 rather than an 04. The requirements for the gates is that they both be inverterrs, and that the second one must be a Schnitt Trigger type. Other than that, they can be any TTL or CMOS variety that matches the rest of your circuits.
A possible issue is that for some logic families, the pull up current capability is much less than the pull down. This means the first gate will have a harder time charging up the capacitor than in the original circuit where it is discharging the capacitor current down to GND. One solution is to use one of the newer, more "stiff" CMOS varieties like the AC or ACT series.
After ***six*** posts, we still have *zero* timing information from you, so we cannot recommend component values.
yes that was the question. As i said it's an integrated design so i can adjust the components as i want. But what would be the threshold values of the schmitt trigger if i have alogic input from 0 to 3.3v?I don't know what "it" is. The circuit I posted, when modified as described, will add a constant time to the width of a negative input pulse, no matter how long or short that pulse is (as long as it is long enough to charge up the cap), stretching a variable width input pulse by a fixed amount of time. Wasn't that the question?
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