pulse width stretching for the "0" output

Thread Starter

iaf

Joined Apr 11, 2019
32
i want to design a circuit for stretching the "0" output of my signal. I have seen the Monostable multivibrator but it stretches the "1" output. is there anyway flipping it or another topology for realizing that?
 

danadak

Joined Mar 10, 2018
3,611
Are you trying to stretch it longer that the clock period ?

Is the D just toggling or sampling another signal for its data input ?

Clock continuous or aperiodic ?

Hand draw a timing diagram or use one of the utilities on the web and post it.

Regards, Dana.
 

Thread Starter

iaf

Joined Apr 11, 2019
32
i want to stretch it longer than the output which is yea longer than the clock (continuous). The D is an output of a comparator
 

djsfantasi

Joined Apr 11, 2010
5,701
So...
How much longer?

  • What’s the frequency of the clock?
  • What’s the desired output length?
  • What happens to the length of the “1” output!
  • If the D output goes high then low while your desired output is “0” then what happens?
 

danadak

Joined Mar 10, 2018
3,611
This is overkill, but requires no code, even though it is an ARM UP inside
and a bunch of other stuff.

Can stretch a pulse from uS to years if you want, and anything in between.

upload_2019-6-12_12-22-20.png

As you can see in right hand columns lots of other resources on chip as well.


Regards, Dana.
 

mvas

Joined Jun 19, 2017
538
i just have a digital output of a D-flipflop and i want to stretch the "0" not the "1"
A very simple idea ...
Stretch-2_mvas.jpg

It works with very short input pulses.

The are also High Speed "Falling Edge" Monostsable Multivibrator IC's
an example IC with a "Falling Edge" input ...
https://assets.nexperia.com/documents/data-sheet/74LVC1G123.pdf


Mods Note:
Please cut the useless space of the circuit before you upload to the forum, the circuit already cut the space.
 
Last edited by a moderator:

Thread Starter

iaf

Joined Apr 11, 2019
32
So...
How much longer?

  • What’s the frequency of the clock?
  • What’s the desired output length?
  • What happens to the length of the “1” output!
  • If the D output goes high then low while your desired output is “0” then what happens?
It seems that there's misunderstanding as the clock is not the output i want to stretch. The output is the D-flipflop output or let's say a digitals out with different pulse lengths. The length of "1" shouldn't be affected and the desired output depends only on the output of the D-flipflop
This is overkill, but requires no code, even though it is an ARM UP inside
and a bunch of other stuff.

Can stretch a pulse from uS to years if you want, and anything in between.

View attachment 179561

As you can see in right hand columns lots of other resources on chip as well.


Regards, Dana.
thanks for your answer but i'm designing this IC so no ready to use ICs
A very simple idea ...
View attachment 179610

It works with very short input pulses.

The are also High Speed "Falling Edge" Monostsable Multivibrator IC's
an example IC with a "Falling Edge" input ...
https://assets.nexperia.com/documents/data-sheet/74LVC1G123.pdf


Mods Note:
Please cut the useless space of the circuit before you upload to the forum, the circuit already cut the space.
The problem that the pulse length is varying and i want this time constant to be added to the original pulse width
 

djsfantasi

Joined Apr 11, 2010
5,701
It seems that there's misunderstanding as the clock is not the output i want to stretch. The output is the D-flipflop output or let's say a digitals out with different pulse lengths.
The problem that the pulse length is varying and ...
There’s the misunderstanding. I didn’t get that the input pulse length varied. The point of my comment is what would happen if you received two pulses during the period of your lengthened pulse? (excuse the rough graphic)
46FADD26-F1FA-4CA5-8B6E-78D2189D30F7.jpeg
 

AnalogKid

Joined Aug 1, 2013
8,140
Here is a grab from the innergoogle, from some old National Semiconductor publication. For your application, reverse D1 and place the R in parallel with the C. The first inverter also can be a 14 rather than an 04. The requirements for the gates is that they both be inverterrs, and that the second one must be a Schnitt Trigger type. Other than that, they can be any TTL or CMOS variety that matches the rest of your circuits.

A possible issue is that for some logic families, the pull up current capability is much less than the pull down. This means the first gate will have a harder time charging up the capacitor than in the original circuit where it is discharging the capacitor current down to GND. One solution is to use one of the newer, more "stiff" CMOS varieties like the AC or ACT series.

After ***six*** posts, we still have *zero* timing information from you, so we cannot recommend component values.



ak
 
Last edited:

Thread Starter

iaf

Joined Apr 11, 2019
32
Here is a grab from the innergoogle, from some old National Semiconductor publication. For your application, reverse D1 and place the R in parallel with the C. The first inverter also can be a 14 rather than an 04. The requirements for the gates is that they both be inverterrs, and that the second one must be a Schnitt Trigger type. Other than that, they can be any TTL or CMOS variety that matches the rest of your circuits.

A possible issue is that for some logic families, the pull up current capability is much less than the pull down. This means the first gate will have a harder time charging up the capacitor than in the original circuit where it is discharging the capacitor current down to GND. One solution is to use one of the newer, more "stiff" CMOS varieties like the AC or ACT series.

After ***six*** posts, we still have *zero* timing information from you, so we cannot recommend component values.



ak
i think that would still have the problem when having longer input pulses. additionally it will be triggered with the raising edge of the input which is another problem
 

AnalogKid

Joined Aug 1, 2013
8,140
I don't know what "it" is. The circuit I posted, when modified as described, will add a constant time to the width of a negative input pulse, no matter how long or short that pulse is (as long as it is long enough to charge up the cap), stretching a variable width input pulse by a fixed amount of time. Wasn't that the question?

ak
 

Thread Starter

iaf

Joined Apr 11, 2019
32
I don't know what "it" is. The circuit I posted, when modified as described, will add a constant time to the width of a negative input pulse, no matter how long or short that pulse is (as long as it is long enough to charge up the cap), stretching a variable width input pulse by a fixed amount of time. Wasn't that the question?

ak
yes that was the question. As i said it's an integrated design so i can adjust the components as i want. But what would be the threshold values of the schmitt trigger if i have alogic input from 0 to 3.3v?
 

djsfantasi

Joined Apr 11, 2010
5,701
Since the entire circuit is 3.3V, the threshold value is... ready for this! “Along with appropriate R and C values, whatever can produce an output pulse of the length that you specify.” Which you haven’t told us. The Schmitt transitions whenever the voltage on the capacitor hits the threshold of the Schmitt inverter. The threshold value is only relevant when sizing the RC network. Since it’s an integrated design, don’t you have control over the threshold voltage? Otherwise you would have picked an IC and told us what the threshold voltage is. And whatever threshold voltage you pick, then you can select the values of R and C to give you your fixed pulse length. Not before.
 

Thread Starter

iaf

Joined Apr 11, 2019
32
alright i got that. well i personally don't know what pulse stretch i would need before simulationg but i would assume 50-100ms with an input pulse width starting from 250-500ns
 

djsfantasi

Joined Apr 11, 2010
5,701
Just teasing you here , @iaf ... But!

<where’s the smack head icon when you need it?>
  • To simulate something, you need to design the simulated circuit.
  • To design the circuit, you need to specify several parameters.
  • To determine the parameters, you need to simulate something. (What?)
Do you see a problem with your statements?

In reality, you have just given a range of the input and output pulse widths. So pick the middle values, create your circuit and perform the simulation. I think people can provide greater feedback when we’re all working in the same set of base assumptions. Perhaps, if you could have responded with these base assumptions earlier, to any of the requests for timing information, we wouldn’t have been at this point after 20 posts. Enough people asked.

Enough said.
 
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