pulse width stretching for the "0" output

mvas

Joined Jun 19, 2017
538
A single gate delay on the initial falling edge
Adds the RC "time delay" only after the rising edge of the pulse
HIGH R + C = Time Delay
Low R + Diode discharges cap very quickly - ie while the Pulse is still low.
Stretches only the "0" pulse

Stretch-3.jpg
 

AnalogKid

Joined Aug 1, 2013
8,227
Depending on the ratio of the minimum input pulse width and the maximum additional time he wants added, there could be a problem with either the Low R value or the current sink capability of whatever is driving this circuit. Still, the second AND input does solve the turn on edge delay problem.

ak
 

eetech00

Joined Jun 8, 2013
1,740
Here is a grab from the innergoogle, from some old National Semiconductor publication. For your application, reverse D1 and place the R in parallel with the C. The first inverter also can be a 14 rather than an 04. The requirements for the gates is that they both be inverterrs, and that the second one must be a Schnitt Trigger type. Other than that, they can be any TTL or CMOS variety that matches the rest of your circuits.

A possible issue is that for some logic families, the pull up current capability is much less than the pull down. This means the first gate will have a harder time charging up the capacitor than in the original circuit where it is discharging the capacitor current down to GND. One solution is to use one of the newer, more "stiff" CMOS varieties like the AC or ACT series.

After ***six*** posts, we still have *zero* timing information from you, so we cannot recommend component values.



ak
Hi

Does the circuit account for the initial HI to LOW input signal (from a D FF) to the first inverter?

eT
 

AnalogKid

Joined Aug 1, 2013
8,227
I don't know what you mean by "account for". In my circuit, the incoming high-to-low moves quickly to the output, slowed only by two gate delays and the time it takes for the first gate to charge up the timing capacitor. Depending on the circuit timing requirements - ***which we still do not know*** - this might be a trivial error. The mvas circuit is better about this, with only a 1-gate propagation delay.

ak
 

eetech00

Joined Jun 8, 2013
1,740
I don't know what you mean by "account for". In my circuit, the incoming high-to-low moves quickly to the output, slowed only by two gate delays and the time it takes for the first gate to charge up the timing capacitor. Depending on the circuit timing requirements - ***which we still do not know*** - this might be a trivial error. The mvas circuit is better about this, with only a 1-gate propagation delay.

ak
Hi

I played with your circuit a little...it didn't seem to trigger correctly. I used the Qbar output of a D flip flop as the input to your circuit.

no worries....probably something I overlooked.

eT
 

mvas

Joined Jun 19, 2017
538
Depending on the ratio of the minimum input pulse width and the maximum additional time he wants added, there could be a problem with either the Low R value or the current sink capability of whatever is driving this circuit. Still, the second AND input does solve the turn on edge delay problem.

ak
The Low R value is specifically there to prevent "Sink Current" from being an issue with the capacitor discharge.
The High R value and the Capacitor creates the delay.
Certainly you could create "bad design" on purpose, but with careful engineering, there is a design that should work.

View attachment 179720
 
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mvas

Joined Jun 19, 2017
538
what are the 2 inputs of the schmidt trigger?
A Schmidt Schmitt type AND Gate ... has hysteresis on the two input pins.
The voltage at which the output changes for a Rising Input Signal is higher than the voltage at which the output changes for a Falling Input Signal.
The difference be the two Trigger Levels is the Hysteresis Band Voltage
Hysteresis is typically used when an Input Signal is derived from a charging or discharging capacitor.
 
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danadak

Joined Mar 10, 2018
3,709
One consideration is do you want a glitch free output when
power is first applied to the circuits ? If so UP usually better
approach. Not all UPs can do that however.

Regards, Dana.
 

mvas

Joined Jun 19, 2017
538
i want to design a circuit for stretching the "0" output of my signal. I have seen the Monostable multivibrator but it stretches the "1" output. is there anyway flipping it or another topology for realizing that?
Are you designing a circuit using IC's or are you designing an IC ?
 

mvas

Joined Jun 19, 2017
538
is there a way to stretch it digitally without using the RC circuit for 100ns only?
Like with a counter that has a high speed clock, that starts counting down on the rising edge ?
A digital delay line?
 
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Thread Starter

iaf

Joined Apr 11, 2019
32
I tried generating a set signal from the rising edge of the pulse i got and feeding it as a set signal for the "counter" which is a d-flipflop with its D connected to the Qn. The problem right now is that the counter will keep counting so i will have half the clock frequency on the output after the pulse goes high as in the simulation. does anyone has a hint how to make it stop after this clock cycle?
counter_01.PNG counter_02.PNG
 
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